Hello,
I have some queries wrt to copying data in external memory on C6670
I'm using EDMA for C6670 memory exchange, it run successfully on simulation but failed to transfer the data when running on the board.
Is there something to take into account when running the example on the board?
CSS Version: 5.0.3
Best Regards,
SRC Buffer(On Board):
External Memory Buffer(On Board):
Data doesn't change,Why?
#include <ti/csl/csl_cacheAux.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <stdint.h>
#include <cerrno>
//EDMA Register
#define EDMA_CC_BASE (0x02700000) // C6670. Check address for other devices.
#define DCHMAP0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0100))
#define QCHMAP0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0000))
#define ESR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1010))
#define DMAQNUM0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0240))
#define QUEPRI *((volatile unsigned int *)(EDMA_CC_BASE + 0x0284))
#define EMCR *((volatile unsigned int *)(EDMA_CC_BASE + 0x0308))
#define EMCRH *((volatile unsigned int *)(EDMA_CC_BASE + 0x030C))
#define QEMCR *((volatile unsigned int *)(EDMA_CC_BASE + 0x0314))
#define CCERRCLR *((volatile unsigned int *)(EDMA_CC_BASE + 0x031C))
#define QWMTHRA *((volatile unsigned int *)(EDMA_CC_BASE + 0x0620))
#define ESR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1010))
#define IPR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1068))
#define ICR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1070))
#define PARAMENTRY0 (0x02704000) // C6670. Check address for other devices.
#define OPT *((volatile unsigned int *)(PARAMENTRY0 + 0x00))
#define SRC *((volatile unsigned int *)(PARAMENTRY0 + 0x04))
#define A_B_CNT *((volatile unsigned int *)(PARAMENTRY0 + 0x08))
#define DST *((volatile unsigned int *)(PARAMENTRY0 + 0x0C))
#define SRC_DST_BIDX *((volatile unsigned int *)(PARAMENTRY0 + 0x10))
#define LINK_BCNTRLD *((volatile unsigned int *)(PARAMENTRY0 + 0x14))
#define SRC_DST_CIDX *((volatile unsigned int *)(PARAMENTRY0 + 0x18))
#define CCNT *((volatile unsigned int *)(PARAMENTRY0 + 0x1C))
//L1 L2 SRAM
#define L1P_SRAM *((unsigned int *)(0x00E00000))
#define L1D_SRAM *((unsigned int *)(0x00F00000))
#define L1P_CFG *((unsigned int *)(0x01840020))
//mode Select
#define L1D_CFG *((unsigned int *)(0x01840040))
#define L2P_SRAM *((unsigned int *)(0x00800000))
//L2 Cache Define
#define L2_CFG *((unsigned int *)(0x01840000))
#define MAR0 *((unsigned int *)(0x01848000))
#define DDR3 (0x80000000)
static signed char srcBuff[512];
static signed char dstBuff[512];
void L1_L2_CacheDisable()
{
Uint16 key;
/* Invalidate the cache before verification */
/* Disable Interrupts */
key = _disable_interrupts();
CACHE_invL1d ((void *)srcBuff, 512, CACHE_WAIT);
CACHE_invL2 ((void *)srcBuff, 512, CACHE_WAIT);
CACHE_invL1d ((void *)dstBuff, 512, CACHE_WAIT);
CACHE_invL2 ((void *)dstBuff, 512, CACHE_WAIT);
_mfence();
/* Re-enable Interrupts. */
_restore_interrupts(key);
}
void EDMA_Test_W()
{
int i;
for(i=0;i<512;i++)
{
srcBuff[i]=0x35;
dstBuff[i]=0x22;
}
L1_L2_CacheDisable();
/* Step 1: EDMA initialization */
QUEPRI=0x10;
QWMTHRA =(16<<8u)|(16 & 0xFF);
EMCR = 0xFFFFFFFF;
CCERRCLR = 0xFFFFFFFF;
/* Step 2: Programming DMA Channel (and Param set) */
DCHMAP0=0x0;
DMAQNUM0=0x0;
OPT = 0x00100000; /* only TCINTEN is set */
SRC = (unsigned int)srcBuff;
A_B_CNT = ((1 << 16u) | (512 & 0xFFFFu)); /* ACNT = 512, BCNT = 1 */
DST = (unsigned int)DDR3;
SRC_DST_BIDX = (512 << 16u) | (512 & 0xFFFFu); /* SRC_BIDX = 512, DST_BIDX = 512 */
LINK_BCNTRLD = (1 << 16u) | 0xFFFFu; /* LINK = 0xFFFF, BCNTRLD = 1 */
SRC_DST_CIDX = 0;
CCNT = 1;
/* Step 3: Triggering the Transfer and Waiting for Transfer Completion */
ESR = 0x1;
while(((IPR) & 0x1) == 0);
/* Transfer has completed, clear the status register. */
ICR=0x01;
/* Transfer is complete. Compare the srcBuff and dstBuff */
L1_L2_CacheDisable();
}
void EDMA_Test_R()
{
/* Step 1: EDMA initialization */
QUEPRI=0x10;
QWMTHRA =(16<<8u)|(16 & 0xFF);
EMCR = 0xFFFFFFFF;
CCERRCLR = 0xFFFFFFFF;
/* Step 2: Programming DMA Channel (and Param set) */
DCHMAP0=0x0;
DMAQNUM0=0x0;
OPT = 0x00100008; /* only TCINTEN is set */
SRC = (unsigned int)DDR3;
A_B_CNT = ((1 << 16u) | (512 & 0xFFFFu)); /* ACNT = 512, BCNT = 1 */
DST = (unsigned int)dstBuff;
SRC_DST_BIDX = (512 << 16u) | (512 & 0xFFFFu); /* SRC_BIDX = 512, DST_BIDX = 512 */
LINK_BCNTRLD = (1 << 16u) | 0xFFFFu; /* LINK = 0xFFFF, BCNTRLD = 1 */
SRC_DST_CIDX = 0;
CCNT = 1;
/* Step 3: Triggering the Transfer and Waiting for Transfer Completion */
ESR = 0x1;
while(((IPR) & 0x1) == 0);
/* Transfer has completed, clear the status register. */
ICR=0x01;
/* Transfer is complete. Compare the srcBuff and dstBuff */
L1_L2_CacheDisable();
}
int main()
{
int i;
EDMA_Test_W();
EDMA_Test_R();
for(i=0;i<16;i++)
{
printf("%d=%x\n",i,dstBuff[i]);
}
}
