chip to chip srio time

jie wang75279

Intellectual 740 points

Hello,

I am testing the bandwidth of the chip to chip srio time.My problem is the bandwidth is 114MB/s which is very low .

The code from my project is from pdk_C6678_1_0_0_12\packages\ti\drv\srio\test\Loopback.

I made some change:

1,I add pll init();I set the mainclk to 1GHZ.

2, I enable the time counter.

3,I change loopback mode to normal mode

    /* Configure SRIO to operate in normal mode. */
     CSL_SRIO_SetNormalMode(hSrio,0);
     CSL_SRIO_SetNormalMode(hSrio,1);
     CSL_SRIO_SetNormalMode(hSrio,2);
     CSL_SRIO_SetNormalMode(hSrio,3);

4,I change PRESCALAR to 6

CSL_SRIO_SetPerscalarSelect(hSrio,6);

5,t_start=clock();

Srio_sockSend();

while(1)

{

Srio_getSockOpt()

}

t_end=clock();

6,Then the result is 114MB/s.

I want to know what 's wrong with my program ,why the bandwidth is so low?

Regards,

wangjie

over 13 years ago

0 RandyP over 13 years ago

TI__Guru* 84110 points

wangjie,

You are not measuring the bandwidth of the SRIO port. You are measuring the throughput of the CSL socket-based software communicating over the SRIO port. Depending on the data you transfer, the overhead may be higher than you expected.

The code you show above is not representative of your working code. It would never exit the while (1) loop to reach the t_end=clock(); statement.

Are you using one lane in 1x mode? At what speed?

RandyP

0 CalvinW over 13 years ago

TI__Prodigy 60 points

Hi Wangjie,

As Randy has indicated in his reply, you seem to be measuring throughput using the PDK LLD so this reply will focus on that.

In order to determine if the throughput you are seeing is inline with what is expected, some more infomation is needed on what you are trying to measure.

1) Which DIO type are you measuring? (NWRITE_R, NWRITE, NREAD...)
2) Which transfer size in bytes are you measuring? (4Byte, 16Byte, 256Byte...)
3) What is the formula that you are using to calculate the throughput?

Please keep the following in mind when measuring the SRIO throughput.

A) SRIO Link Gbaud = Port Width * Lane speed (This is the link rate, not the data rate)
B) The 8b/10b hardware encoding that SRIO uses will have a 20% overhead on the data rate.
C) Different transfer types (NWRITE, NREAD...) have different transfer overheads as well.
D) Smaller packet sizes take more processing overhead to send.

For the PDK release (PDK_1_0_0_12) that you are using there is a mistake in the PLL value that was specified. This is corrected in PDK_1_0_0_14, but in that PDK release the value is for 3.125Gbaud.

To set the lane rate to 5.0Gbaud for the C6678 PDK please do the following:

In device_srio_loopback.c:

    Please change this line:
      CSL_BootCfgSetSRIOSERDESConfigPLL (0x235);
    To this line to be at 5.0Gbaud:
      CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

After recompiling with the change above, the loopback application will now be set for a Port Width of 1 (1 lane) and a Lane Rate of 5.0Gbaud assuming that you have only changed what is shown in your posting.

To calculate the max data rate per second for this setting please see the following:

Max data rate = 1 * 5.0Gbaud * .8 (The .8 is to account for the 8b/10b hardware encoding overhead)
Max data rate = 4.0Gbaud or 4000 megabits/sec. or 500 megaBytes/sec.
(This is the max rate at which data can be pushed across the link for this setting. Packet overhead will lower the data rate even more.)

The answers you give to the three questions at the top will help determine if the transfer rate you are seeing is in line with what is expected for the link rate, packet size, and transfer type that you are measuring.

Best Regards,
Calvin

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