Hi,
in our design the AM6421 is connected to a DDR4 memory, which should be tested in connectivity test mode with Boundary Scan.
In the BSDL file of the AM6421 (AM64_AM243.bsd) , some pins of the memory interface (i.e ddr_dqs0 and ddr_dqs1) are marked as "differential" (excerpt of the BSDL file):
attribute PORT_GROUPING of AM64 : entity is
"Differential_Voltage ( "&
"(serdes0_tx0_p, serdes0_tx0_n), "&
"(ddr0_ck0, ddr0_ck0_n), "&
"(ddr0_dqs0, ddr0_dqs0_n), "&
"(ddr0_dqs1, ddr0_dqs1_n)) ";
As a result, there is no possibillity to drive (or sense) the ddr_dqs0_n and ddr_dqs1_n signal pins indepedent of their differential co-partner ddr_dqs0 and ddr_dqs1. In normal case, this should not be necessary and therefore no problem.
However, if the connected DDR4 memory is in connectivity test mode, this is not the case: The differential signal pairs (driven from the DDR4 memory) are no longer mandatory inverse to each other anymore.
This leads to my first question: If, for example, ddr_dqs0 and ddr_dqs0_n are both simultaneously low (or high), what will be the value of the single boundary scan sensing cell ? Is either the signal value at ddr_dqs0 dominant or the signal value of ddr_dqs0_n, or is the result even random ?
And, second question: Is there any workaround ?
Unfortunately, this behaviour leads to a restricted test depth of the DDR4 memory connections.
Best regards,
Stefan