ddr2 on OMAPL138

Are you using CCS? If so open up the memory window to 0xC0000000. Try writing values in there to confirm if the odd addresses are not functioning.

Jeff

Tnank you very much,Jeff.

Yes,I can see the 0xc0000000~0xc000XXXX in memery view.0xc0000000,0xc000008,0xc0000010 ... were functioning.0xc0000004,0xc000000A,0xc0000014 were not.The ddr2 chip is K4T51163QG-HCF7(512M).

And my ddr registers come here:

   // config ddr timing.
   DDR->DDRPHYCTL1 = 0x000000C4;
   DDR->SDCR = 0x0893C622;
   DDR->SDCR &= ((DDR->SDCR & 0xFF0FFFFF) | 0x00800000);
   DDR->SDCR = ((DDR->SDCR & 0xFF0FFFFF) | 0x02000000);
   DDR->SDCR &= (~0x00008000);
  
   DDR->SDTIMR1 = 0x20923A89;
   DDR->SDTIMR2 = 0x0015C720;
   DDR->SDCR2 = 0x0;
   DDR->SDRCR = 0x00000492;
  
   // set ddr2 to sync reset.
   SETBIT(DDR->SDRCR, 0xC0000000);
  
   // sync reset the ddr clock.
   EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_SYNCRESET);
  
   // enable the clock.
   EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_ENABLE);
  
   // disable self refresh.
   CLRBIT(DDR->SDRCR, 0xC0000000);

As I know,ddr2 is 16 bits wide data bus.Do it need special setting when  writing or reading date in the memery ?

Best regards for any help.

Yu

I have some clues here .In the cmd file,if the sections setting as below,The read write are ok.But if when I added dsp/bios,the program can't run.It stops in the initialization.I don't know why.I think ddr2 may need special SECTIONS setting.

MEMORY
{
    IRAM:       o = 0x80000000  l = 0x00020000  /* 128 kBytes L3RAM */
    DRAM:       o = 0xC2000000  l = 0x02000000  /*  64 MBytes SDRAM */
 AEMIF:      o = 0x62000000  l = 0x02000000   /*  32 MBytes CS3 EMIF  */
}

SECTIONS
{
/*    .bss        >   IRAM
    .cinit      >   IRAM
    .cio        >   IRAM
    .const      >   IRAM
    .stack      >   IRAM
    .sysmem     >   IRAM
    .text       >   IRAM
    .DRAM       >   IRAM
    .far        >   IRAM
    .switch     >   IRAM
 .aemif_mem  >   AEMIF
*/
    .bss        >   DRAM
    .cinit      >   DRAM
    .cio        >   DRAM
    .const      >   DRAM
    .stack      >   DRAM
    .sysmem     >   DRAM
    .text       >   DRAM
    .DRAM       >   DRAM
    .far        >   DRAM
    .switch     >   DRAM  
 .aemif_mem  >   AEMIF   
}

So without DSP/BIOS your DDR configuration works and you can read and write to all addresses in the memory window? But when you include DSP/BIOS half the memory breaks?

I don't believe DSP/BIOS touches the DDR configuration, but go ahead and check the DDR config registers at 0xB0000000 in both cases and make sure the settings are identical.

Jeff

Thanks ,Jeff.

DSP/BIOS doesn't touches the DDR configuration,but the sections setting will make ddr2 wrong.

The setting below is ok:

MEMORY
{
    IRAM:       o = 0x80000000  l = 0x00020000  /* 128 kBytes L3RAM */
    DRAM:       o = 0xC2000000  l = 0x02000000  /*  64 MBytes SDRAM */
 AEMIF:      o = 0x62000000  l = 0x02000000   /*  32 MBytes CS3 EMIF  */
}

SECTIONS
{
/*    .bss        >   IRAM
    .cinit      >   IRAM
    .cio        >   IRAM
    .const      >   IRAM
    .stack      >   IRAM
    .sysmem     >   IRAM
    .text       >   IRAM
    .DRAM       >   IRAM
    .far        >   IRAM
    .switch     >   IRAM
 .aemif_mem  >   AEMIF
*/ 
    .bss        >   DRAM
    .cinit      >   DRAM
    .cio        >   DRAM
    .const      >   DRAM
    .stack      >   DRAM
    .sysmem     >   DRAM
    .text       >   DRAM
    .DRAM       >   DRAM
    .far        >   DRAM
    .switch     >   DRAM   
 .aemif_mem  >   AEMIF   
}

but the setting below is not:

MEMORY
{
    IRAM:       o = 0x80000000  l = 0x00020000  /* 128 kBytes L3RAM */
    DRAM:       o = 0xC2000000  l = 0x02000000  /*  64 MBytes SDRAM */
 AEMIF:      o = 0x62000000  l = 0x02000000   /*  32 MBytes CS3 EMIF  */
}

SECTIONS
{
    .bss        >   IRAM
    .cinit      >   IRAM
    .cio        >   IRAM
    .const      >   IRAM
    .stack      >   IRAM
    .sysmem     >   IRAM
    .text       >   IRAM
    .DRAM       >   IRAM
    .far        >   IRAM
    .switch     >   IRAM
 .aemif_mem  >   AEMIF

/*    .bss        >   DRAM
    .cinit      >   DRAM
    .cio        >   DRAM
    .const      >   DRAM
    .stack      >   DRAM
    .sysmem     >   DRAM
    .text       >   DRAM
    .DRAM       >   DRAM
    .far        >   DRAM
    .switch     >   DRAM   
 .aemif_mem  >   AEMIF   */
}

It seems that the memery setting may affect the DDR2.

I think I need to check the ddr2 register carefully.

Can you give a brief description on what you changed to solve the problem?

Jeff