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AM6421: Enabling DMA for main_spi1 in device tree (linux)

Torsten Bitterlich
Prodigy 40 points
Part Number: AM6421


Hello,

I want to use the SPI device main_spi1 as a slave. For main_spi0 this is working, however for main_spi0 DMA is enabled in the device tree (k3-am64-main.dtsi):

    main_spi0: spi@20100000 {
        compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
        reg = <0x00 0x20100000 0x00 0x400>;
        interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
        clocks = <&k3_clks 141 0>;
        dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
        dma-names = "tx0", "rx0";
        status = "disabled";
    };

Beside that I extended main_spi0 with the settings required for working as an spi slave in my custom device tree:

&main_spi0 {

    status = "okay";

    #address-cells = <0>;
    #size-cells = <0>;
    spi-slave;

    pinctrl-names = "default";
    pinctrl-0 = <&main_spi0_pins_default>;

    slave {
        reg = <0>;
        compatible = "rohm,dh2228fv";
        spi-max-frequency = <4000000>;
    };
};

For main_spi1 the dmas and the dma-names entries are missing. I'm aware that the dma-names need to be called "tx0" and "rx0" for the first chip select.

Where does the description for the dmas (0xc300 0, 0x4300 0) for the spi0 come frome and what is required for main_spi1 dmas definition?

Thank you!

  • 0
    Prodigy 40 points

    Hello,

    found out by myself. The numbers correlate to DMA channels, which are described in this header of the mcu-sdk for am64:

    mcu_plus_sdk/source/drivers/udma/soc/am64x_am243x/udma_soc.h

    /*
     * PDMA MAIN0 MCSPI RX Channels
     */
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX    (0x4300U + 0U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX    (0x4300U + 1U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX    (0x4300U + 2U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX    (0x4300U + 3U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX    (0x4300U + 4U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX    (0x4300U + 5U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX    (0x4300U + 6U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX    (0x4300U + 7U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX    (0x4300U + 8U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX    (0x4300U + 9U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX    (0x4300U + 10U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX    (0x4300U + 11U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX    (0x4300U + 12U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX    (0x4300U + 13U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX    (0x4300U + 14U)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX    (0x4300U + 15U)

    /* ... */

    /*
     * PDMA MAIN0 MCSPI TX Channels
     */
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
    #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

    So the correct settings for mcspi1 as a slave are:

    &main_spi1 {

        compatible = "ti,am654-mcspi","ti,omap4-mcspi";
        reg = <0x00 0x20110000 0x00 0x400>;
        interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
        clocks = <&k3_clks 142 0>;
        dmas = <&main_pktdma 0xc304 0>, <&main_pktdma 0x4304 0>;
        dma-names = "tx0", "rx0";

        status = "okay";

        #address-cells = <0>;
        #size-cells = <0>;
        spi-slave;

        pinctrl-names = "default";
        pinctrl-0 = <&main_spi1_pins_default>;

        slave {
            reg = <0>;
            compatible = "rohm,dh2228fv";
            spi-max-frequency = <4000000>;
        };
    };