TDA4VH-Q1: C71x double precision dsplib

Hi Tony,

Currently, there is no roadmap to add functions or add datatypes to existing functions for the C7x libraries that were delivered in the 9.2 RTOS SDK release. 

If you have a customer who requires using a different datatype, the source code for the C7x libraries is available, and the customer can add support for their specific datatype if datatype conversion is not possible. 

Asha

Hi Tony, 

I went back and looked at the code after your email. DSPLIB_svd does have double precision supported, it is just not included on the performance summary sheet. 

There are test cases implemented for double precision (see test cases with precision of DSPLIB_FLOAT64 that are defined in DSPLIB_svd_idat.c). Sorry for the confusion on this point.

Regarding your second point,

BTW, they evaluated the SP version C7x function, the speed is not quick enough as expected. They ask if the SVD function in the DSPlib is optimized?

Kernels that we have provided should be fully optimized for the architecture. When they say the performance is "not as expected," can you clarify this point? What are they trying to compare the performance to?

Best,

Asha

Hi Asha,

Is there a ARM version SVD implementation, especially performance data?

Hi Asha,

Customer uses 6 order SVD only, can you help to provide the benchmark of it? especially for double float point? have single float point for comparison would be better.

Hi Tony,

When you are referring to 6 order SVD, are you referring to a SVD with a 6x6 matrix?

If so, the customer can run test case #49 for double precision and test case #14 for single floating point precision.

Best,

Asha

Hi Asha,

#1. According to the user guide, how to run the .out in no boot mode? did not find a guide, there should be a script to initialize board before download .out

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/09_02_00_05/exports/docs/dsplib_09_02_00_04/docs/user_guide/build_instructions_linux.html

Run

• To run DSPLIB kernels on a PC:
  • bin/Release/test_DSPLIB_<kernel_name>_<device>_x86_64
    OR
    bin/Debug/test_DSPLIB_<kernel_name>_<device>_x86_64
    • Ex:
      bin/Release/test_DSPLIB_sqr_C7120_x86_64
• To run DSPLIB kernels for target
  • To reproduce numbers given in the datasheet, run the .out program on the EVM in No Boot Mode

#2. If I boot up board to linux, then connect C71x and download .out, it report error at the end

C71X_0: File Loader: Verification failed: Values at address 0x0000000070700000 do not match Please verify target memory and memory map.
C71X_0: GEL: File: C:\Users\a0283043\Desktop\test_DSPLIB_svd_C7120.out: a data verification error occurred, file load failed.

#3. It take very long time to launch CCS TDA4VH configuration, download .out is also very slow. How do you run test .out, is it slow or acceptable on your side?

Hi Tony,

Tony Tang said:

#1. According to the user guide, how to run the .out in no boot mode? did not find a guide, there should be a script to initialize board before download .out

This process is documented in the RTOS SDK documentation. See section 7.3.2. Step 3: Load RTOS/baremetal application binaries thru CCS

Tony Tang said:

#2. If I boot up board to linux, then connect C71x and download .out, it report error at the end

The DSPLIB library release was tested as a baremetal library - not with the Linux boot flow. I'd imagine the issue is that the linker files used to build the DSPLIB library conflict with default linker files used to create the Linux boot flow, which is why you would see memory map errors. 

Tony Tang said:

#3. It take very long time to launch CCS TDA4VH configuration, download .out is also very slow. How do you run test .out, is it slow or acceptable on your side?

How long is a long time in this case? On my end, loading the target configuration does not take more than a few seconds. The loading of the .out file might be slower if many test cases are run together, but it does not take a significant amount of time ( < 1 minute). 

Best,

Asha

Asha Bhandarkar said:

the customer can run test case #49 for double precision and test case #14 for single floating point precision.

Finally I run up the dsplib_svd on TDA4VM EVM, get below result, how to interpret the output?

6177.dsplib_svd_test_result.txt

are the console output of test 14 for single float and test 49 for double float precision result?

How to Interpret cold cycle, warm cycles, warm cycles WRB?

Test Pass!
Test    0: Cold Cycles =     3767, Warm Cycles =     2178, Warm Cycles WRB =     2225
Test   14: Cold Cycles =    60108, Warm Cycles =    57954, Warm Cycles WRB =    58009
Test   49: Cold Cycles =    78972, Warm Cycles =    76077, Warm Cycles WRB =    76153
Test   50: Cold Cycles =   132887, Warm Cycles =   129085, Warm Cycles WRB =   129222

Hi Asha,

From the result, 6x6 takes up to 57954 cycles, it is 57.954us on 1GHz C7x DSP.

Customer tested 6x6 SVD on TDA4VH A72 under Linux, it takes only ~20us, How do you think about the result?

Hi Tony,

Sorry for the delay in response - TI had a US holiday on 5/27. 

Generally I can't comment too much on the comparison as we have not done any performance comparisons between A72 and C7x for the DSPLIB functions. Could you provide more information on what ARM library and SVD implementation the customer is using to make this comparison? Then I might be able to provide better feedback. 

Best,

Asha

Asha Bhandarkar said:

How long is a long time in this case? On my end, loading the target configuration does not take more than a few seconds. The loading of the .out file might be slower if many test cases are run together, but it does not take a significant amount of time ( < 1 minute).

What emulator are you using? and the computer configuration?

Hi Tony,

I'm running CCS 12.4 on Ubuntu 22.04. I am using XDS110 to connect. If you/the customer is having specific issues with CCS, I would recommend starting a new thread for that so the issue can go to our CCS experts. 

Best,

Asha