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TDA4VH-Q1: The CPU suddenly stops working when the junction temperature reaches 122 degrees Celsius

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH



        There is a problem with the high temperature test now: when the ambient temperature rises to 105 degrees Celsius, the junction temperature will be around 122 degrees Celsius. After running in this environment for a period of time (possibly 10 minutes, maybe half an hour, uncertain), the serial port will suddenly not print, the system will stop, and a flashing program will not flash. When the ambient temperature drops to around 80 degrees Celsius, we can see the startup printing on the CPU serial port (with uboot, the kernel starts printing, indicating that the system has restarted); This phenomenon may not occur on all boards, but if this phenomenon has occurred, the same environment will also reappear on this board.

There are the following clues


【1】 Method for obtaining junction temperature:

           cat /sys/class/thermal/thermal_zone*/temp
【2】 When the ambient temperature drops to around 80 degrees Celsius, uboot will start; After starting, check the junction temperature at that time, which is still over 100 degrees Celsius.
【3】 Cooling to 80 degrees will restart. No cooling, no restarting. 
【4】 When the phenomenon occurs, the value of registers 0x5a -0x6c in PMIC (TPS6594133ARWERQ1) remains the same as before
【6】 Checked the reset signal and found that when cpu was stop working, the reset signal was not pulled low;

【7】When the problem occurs, the Linux kernel does not report any errors or print

How should I solve this problem?

The follow txt is pmic register.

 the pmic register value
 
 ==0x5a==
 
 0x9a
 
 ==0x5b==
 
 0x00
 
 ==0x5c==
 
 0x00
 
 ==0x5d==
 
 0x00
 
 ==0x5e==
 
 0x00
 
 ==0x5f==
 
 0x01
 
 ==0x60==
 
 0x40
 
 ==0x61==
 
 0x00
 
 ==0x62==
 
 0x00
 
 ==0x63==
 
 0x00
 
 ==0x64==
 
 0x00
 
 ==0x65==
 
 0x02
 
 ==0x66==
 
 0x01
 
 ==0x67==
 
 0x00
 
 ==0x68==
 
 0x00
 
 ==0x69==
 
 0x04
 
 ==0x6a==
 
 0x00
 
 ==0x6b==
 
 0x00
 
 ==0x6c==
 
 0x00
 

the follow log is cpu's console log

cpu_console_log.log

 

  • Hi, Any updates here?

    Regards

    Zekun

  • Zekun,

    The thermal sensor has both interrupts and a reset. The reset threshold is controlled by:

    MAXT_OUTRG_ALERT_THR0: This defines the global max temperature out of range safe sample value. 
    MAXT_OUTRG_ALERT_THR This defines the global max temperature out of range sample value. 
    ANY_MAXT_OUTRG_ALERT_EN This bit when enabled will cause the VTM's output therm_maxtemp_outrange_alert to be driven high, if any of the sources for the maxt_outrg_alert, is set high. Whenever all the maxt_outrg_alert enabled sensor alerts, out of the 8 possible are back to 0 then the output, therm_maxtemp_outrange_alert, will also return to 0. 

    Kevin

  • Hi, Kevin

    Understand. From your words, you refer to the SOC got reset threshold and reset.

    >>【2】 When the ambient temperature drops to around 80 degrees Celsius, uboot will start; After starting, check the junction temperature at that time, which is still over 100 degrees Celsius.
    >>【3】 Cooling to 80 degrees will restart. No cooling, no restarting. 

    But from the scenario, when the temperature is 100, and not cool down to 80 degrees, it won't get reset. 

    Until it cool down to 80degrees, it will get reset. 

    Regards

    Zekun

  • Zekun,

    Check the values of the bitfields in order to determine if these finding match to what is programmed.

    Kevin

  • Hi, gaojun,

    Could you please help to dump VTM related register listed in TDA4VH TRM package (https://www.ti.com/lit/zip/spruj52) on the board with above observed phenomena? It's better to dump registers at below point 2 and 3 separately. Thanks.

    【2】 When the ambient temperature drops to around 80 degrees Celsius, uboot will start; After starting, check the junction temperature at that time, which is still over 100 degrees Celsius.
    【3】 Cooling to 80 degrees will restart. No cooling, no restarting. 

    WKUP_VTM0 Length Register Offset Register Name
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0000h 32 0h VTM_VTM_PID
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0004h 32 4h VTM_VTM_DEVINFO_PWR0
    4204 0204h 32 204h VTM_VTM_GT_TH1_INT_RAW_STAT_SET
    4204 0204h 32 204h VTM_VTM_GT_TH1_INT_RAW_STAT_SET
    4204 0204h 32 204h VTM_VTM_GT_TH1_INT_RAW_STAT_SET
    4204 0208h 32 208h VTM_VTM_GT_TH1_INT_EN_STAT_CLR
    4204 0208h 32 208h VTM_VTM_GT_TH1_INT_EN_STAT_CLR
    4204 0208h 32 208h VTM_VTM_GT_TH1_INT_EN_STAT_CLR
    4204 0214h 32 214h VTM_VTM_GT_TH1_INT_EN_SET
    4204 0214h 32 214h VTM_VTM_GT_TH1_INT_EN_SET
    4204 0214h 32 214h VTM_VTM_GT_TH1_INT_EN_SET
    4204 0218h 32 218h VTM_VTM_GT_TH1_INT_EN_CLR
    4204 0218h 32 218h VTM_VTM_GT_TH1_INT_EN_CLR
    4204 0218h 32 218h VTM_VTM_GT_TH1_INT_EN_CLR
    4204 0224h 32 224h VTM_VTM_GT_TH2_INT_RAW_STAT_SET
    4204 0224h 32 224h VTM_VTM_GT_TH2_INT_RAW_STAT_SET
    4204 0224h 32 224h VTM_VTM_GT_TH2_INT_RAW_STAT_SET
    4204 0228h 32 228h VTM_VTM_GT_TH2_INT_EN_STAT_CLR
    4204 0228h 32 228h VTM_VTM_GT_TH2_INT_EN_STAT_CLR
    4204 0228h 32 228h VTM_VTM_GT_TH2_INT_EN_STAT_CLR
    4204 0234h 32 234h VTM_VTM_GT_TH2_INT_EN_SET
    4204 0234h 32 234h VTM_VTM_GT_TH2_INT_EN_SET
    4204 0234h 32 234h VTM_VTM_GT_TH2_INT_EN_SET
    4204 0238h 32 238h VTM_VTM_GT_TH2_INT_EN_CLR
    4204 0238h 32 238h VTM_VTM_GT_TH2_INT_EN_CLR
    4204 0238h 32 238h VTM_VTM_GT_TH2_INT_EN_CLR
    4204 0244h 32 244h VTM_VTM_LT_TH0_INT_RAW_STAT_SET
    4204 0244h 32 244h VTM_VTM_LT_TH0_INT_RAW_STAT_SET
    4204 0244h 32 244h VTM_VTM_LT_TH0_INT_RAW_STAT_SET
    4204 0248h 32 248h VTM_VTM_LT_TH0_INT_EN_STAT_CLR
    4204 0248h 32 248h VTM_VTM_LT_TH0_INT_EN_STAT_CLR
    4204 0248h 32 248h VTM_VTM_LT_TH0_INT_EN_STAT_CLR
    4204 0254h 32 254h VTM_VTM_LT_TH0_INT_EN_SET
    4204 0254h 32 254h VTM_VTM_LT_TH0_INT_EN_SET
    4204 0254h 32 254h VTM_VTM_LT_TH0_INT_EN_SET
    4204 0258h 32 258h VTM_VTM_LT_TH0_INT_EN_CLR
    4204 0258h 32 258h VTM_VTM_LT_TH0_INT_EN_CLR
    4204 0258h 32 258h VTM_VTM_LT_TH0_INT_EN_CLR
    4204 0100h 32 100h + (j *20h); where j = 0 to 7 VTM_VTM_VD_DEVINFO_j
    4204 0100h 32 100h + (j *20h); where j = 0 to 7 VTM_VTM_VD_DEVINFO_j
    4204 0100h 32 100h + (j *20h); where j = 0 to 7 VTM_VTM_VD_DEVINFO_j
    4204 0100h 32 100h + (j *20h); where j = 0 to 7 VTM_VTM_VD_DEVINFO_j
    4204 0100h 32 100h + (j *20h); where j = 0 to 7 VTM_VTM_VD_DEVINFO_j
    4204 0104h 32 104h + (j *20h); where j = 0 to 7 VTM_VTM_VD_OPPVID_j
    4204 0104h 32 104h + (j *20h); where j = 0 to 7 VTM_VTM_VD_OPPVID_j
    4204 0104h 32 104h + (j *20h); where j = 0 to 7 VTM_VTM_VD_OPPVID_j
    4204 0104h 32 104h + (j *20h); where j = 0 to 7 VTM_VTM_VD_OPPVID_j
    4204 0104h 32 104h + (j *20h); where j = 0 to 7 VTM_VTM_VD_OPPVID_j
    4204 0108h 32 108h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_STAT_j
    4204 0108h 32 108h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_STAT_j
    4204 0108h 32 108h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_STAT_j
    4204 0108h 32 108h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_STAT_j
    4204 0108h 32 108h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_STAT_j
    4204 010Ch 32 10Ch + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_SET_j
    4204 010Ch 32 10Ch + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_SET_j
    4204 010Ch 32 10Ch + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_SET_j
    4204 010Ch 32 10Ch + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_SET_j
    4204 0110h 32 110h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_CLR_j
    4204 0110h 32 110h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_CLR_j
    4204 0110h 32 110h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_CLR_j
    4204 0110h 32 110h + (j *20h); where j = 0 to 7 VTM_VTM_VD_EVT_SEL_CLR_j
    4204 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4204 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4204 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4204 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4204 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4204 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 0308h 32 308h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_STAT_j
    4204 030Ch 32 30Ch + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH_j
    4204 030Ch 32 30Ch + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH_j
    4204 030Ch 32 30Ch + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH_j
    4204 030Ch 32 30Ch + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH_j
    4204 030Ch 32 30Ch + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH_j
    4204 0310h 32 310h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH2_j
    4204 0310h 32 310h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH2_j
    4204 0310h 32 310h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TH2_j
    4205 0008h 32 8h VTM_VTM_CLK_CTRL
    4205 0008h 32 8h VTM_VTM_CLK_CTRL
    4205 0008h 32 8h VTM_VTM_CLK_CTRL
    4205 0008h 32 8h VTM_VTM_CLK_CTRL
    4205 000Ch 32 Ch VTM_VTM_MISC_CTRL
    4205 000Ch 32 Ch VTM_VTM_MISC_CTRL
    4205 000Ch 32 Ch VTM_VTM_MISC_CTRL
    4205 0010h 32 10h VTM_VTM_MISC_CTRL2
    4205 0010h 32 10h VTM_VTM_MISC_CTRL2
    4205 0010h 32 10h VTM_VTM_MISC_CTRL2
    4205 0010h 32 10h VTM_VTM_MISC_CTRL2
    4205 0010h 32 10h VTM_VTM_MISC_CTRL2
    4205 0020h 32 20h VTM_VTM_SAMPLE_CTRL
    4205 0020h 32 20h VTM_VTM_SAMPLE_CTRL
    4205 0020h 32 20h VTM_VTM_SAMPLE_CTRL
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0300h 32 300h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_CTRL_j
    4205 0304h 32 304h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TRIM_j
    4205 0304h 32 304h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TRIM_j
    4205 0304h 32 304h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TRIM_j
    4205 0304h 32 304h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TRIM_j
    4205 0304h 32 304h + (j *20h); where j = 0 to 7 VTM_VTM_TMPSENS_TRIM_j

     

    Br, Tommy