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VTP IO calibration in AM18x bootloader

Takahiro Ogo
Genius 5940 points
Other Parts Discussed in Thread: AM1808

Hi,
I have a question regarding DDR configuration in AIS Boot.

Does AM18x Bootloader perform VTP IO calibration when booting the boot image?
(I'm setting DDR configuration when generating boot images.)

I guess it is working from VTPIO_CTL register value.
-Takao

 

 

  • 0
    TI__Mastermind 27585 points

    Yes the bootloader will perform the VTP calibration automatically.

    Jeff

  • 0 in reply to jc-ti
    Genius 5940 points

    Hi, Jeff

    Thank you for the reply.
    However, I'm yet inadequately understood.

    After booting AIS boot image, VTPIO_CTL was 0x0018e1b7.
    This values are
     POWERDN=0


    If bootloader pefrome the VTP calibration as described "DDR User's Guide",
    I think VTPIO_CTL must be
     POWERDN=1

    Why is it different?
    And DDR_ZP pin remained output pulse by the VTP calibration in bootloader. (POWERDN=0 in VTPIO_CTL)
    If I peform DDR configuraton by AM1808.gel of LogicPD, DDR_ZP was not output pulse. (POWERDN=1 in VTPIO_CTL)

    How does bootloader perform VTP calibration in bootloader?
    And, Is it right?

     
    #Please confirm the 「2.13.1 Initializing Following Device Power Up or Reset」in SPRUFU3B.pdf.
    VTP IO calibration is described as below

     3. Perform VTP IO calibration:
      (a) Clear POWERDN bit in the VTP IO control register (VTPIO_CTL).
      (b) Clear LOCK bit in VTPIO_CTL.
      (c) Pulse CLKRZ bit in VTPIO_CTL:
       (i) Set CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
       performing a read-modify-write of VTPIO_CTL in the next step).
       (ii) Clear CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
       performing a read-modify-write of VTPIO_CTL in the next step).
       (iii) Set CLKRZ bit.
      (d) Poll READY bit in VTPIO_CTL until it changes to 1.
      (e) Set LOCK bit in VTPIO_CTL. VTP is locked and dynamic calibration is disabled.
      (f) Set POWERDN bit in VTPIO_CTL to save power.

  • 0 in reply to Takahiro Ogo
    TI__Mastermind 27585 points

    The POWERDN bit may be set to conserve power, but it is not required. The current bootloader doesn't perform this step, but the user code may perform this step later if power is a concern.

    Jeff

     

  • 0 in reply to jc-ti
    Genius 5940 points

    Hi Jeff,

    Thank you for the reply. 

     

    I have one more question.

    In case of rev2.1, Bootlloader Application Note is described as below. (http://www.ti.com/lit/an/spraba5b/spraba5b.pdf)

     

    E.4 ROMID: D800K008, Silicon Revision 2.1

    • Update DDR Configure Function Execute to skip VTP calibration if it is already done

     

    Where are bootloader checking to skip VTP calibration?

    I guess bootloader is checking POWERDN bit of VTPIO_CTL register.

     

    -Takao

  • 0 in reply to Takahiro Ogo
    TI__Mastermind 27585 points

    Yes it is checking the POWERDN bit of the VTPIO_CTL register.

    However it turns out that there is no issue with performing VTP calibration multiple times if done according to the user guide process. The bootloader does not clear the LOCK bit of the VTPIO_CTL register at the start, which is why it is unable again once the LOCK bit is set.

    Jeff

  • 0 in reply to jc-ti
    Genius 5940 points

    Thank you very much. You helped me a lot.

    -Takao