Hello TI,
I am developing a low level driver for Serdes 2L and I using the TI PDK driver as a reference.
In the function CSL_serdesRefclkSel there is a cycle delay of 1us which I cannot trace to the documentation.
/* REFCLK_DIG_SEL = pma_cmn_refclk_int */
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_RST),25,24,0x1);
/* PLL0_REFCLK_SEL: Selects pma_cmn_refclk_int as reference clock source */
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_RST),28,28,0x1);
/* PLL1_REFCLK_SEL: Selects pma_cmn_refclk1_int as reference clock source. */
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_RST),29,29,0x1);
/* Wait 1us before writing to CMN registers */
CSL_serdesCycleDelay(1000);
Why is this delay needed? Does it need to be 1us?
Thank you,
Marina
