Other Parts Discussed in Thread: TDA4VH
Hi TI Experts,
Customer is working on TDA4AP SDK9.2.
Their soft realtime (cycle time 1-12 ms) and non realtime threads are running on one quad core A72 cluster. The hard realtime software (cycle time < 1ms) is running on R5F cores.
Their question refers to A72 cluster:
They observe that non-real-time processes sporadically have a major influence on their real-time processes. The observation is that the real-time processes sporadically have significantly longer execution times and as a result cyclic deadlines are missed.
Their explanation for this is that the L2 cache is shared across the entire quad cluster and therefore, in the event of cache misses in cyclic real-time processes, significantly longer execution times can occur due to slower RAM accesses.
Hence, customers would like to know could non realtime threads use L3 cache while realtime threads use L2 cache at the same time for A72 cluster?
If yes, could you provide some guide to do that?
If not, do you have any other suggestion like core isolation to help them achieve better performance?
Thanks in advance!
Kevin
