SK-TDA4VM: USB2.0 /3.0 Compliant test

Jaecheon,

could you try the below method to put the SoC USB2.0 in the test mode?

https://software-dl.ti.com/processor-sdk-linux/esd/AM57X/08_02_01_00/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/USB/DWC3.html

for the USB3.0, the TX compliance requires 3 different test patterns. LFPS, CP0 and CP1.

We enable LFPS in our SERDES diagnostics bare metal code. CP0 I put the SoC in a loopback mode, send in the CP0 pattern from the BERT and capture the output on the scope. CP1 is generated within the SERDES code as well. Its a clock signal with SSC added. I used Lecroy scope which had the 3.0 compliance test suite to capture these waveforms and process them.

RX JTOL is done using the BERT into the device and device TX connected back to the BERT which analyzes them. The additional Sj/ Rj/ Tj are added by the BERT (after going through calibration on the Keysight scope).