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AM62P-Q1: Parameter clarification on DDR configuration using Sysconfig

Part Number: AM62P-Q1
Other Parts Discussed in Thread: SK-AM62P-LP, SYSCONFIG, AM62P

Hi guys. 

We are designing a custom board based on AM62P54.

As starting reference we have used the EVM board SK-AM62P-LP

The main memory is LPDDR4 (micron MT53E512M32D1ZW-046AUT:B).

Configuring timing for the memory above is quite straight forward using SYSCONFIG DDR Subsystem Register Configuration (0.10.01).

But There are a couple of parameter which are disabled in default configuration used on evm board:

Enable Periodic WDQ leveling

Periodic ZQ calibration

On AM62P TRM or Datasheet i haven't found too much about this kind of setting and when they should be activated.

Considering this parameter involves ZQ calibration and Write leveling i suppose they should be useful if my system must function over a wide temperature range.. am i right?

As design constraints our board must function over -40° to 85° (ambient).. Should i set as active the two parameter listed above? there are drawbacks using them active?

Thanks for your reply!

Have a nicew day!

  • Hi Luca,

    yes you are correct.  These parameters are optional to enable for customers, but typically would be enabled if you have a wide operating temp range (ie -40 to 125C).  ZQ calibration would just enable periodic calibration on the memory side (periodic ZQ calibration for the processor IO is always enabled).  Enabling this would incur a very slight hit in performance, since a calibration command would be sent to the memory every 256ms.

    Similarly, WDQ leveling would enable periodic WDQ leveling, which in our testing has been shown to be necessary when operating up to 125C.  We have gotten stable operation with this disabled when operating below 85C.  But you would need to perform your own stress tests to determine if this is necessary on your board.  This training executes every 71ms and takes a few microseconds to complete.  When enabled, we have seen this cause issues with realtime performance on some systems.

    Regards,

    James   

  • All clear! Thank you very much!