AM62A7: SW Changes Required for QSPI Flash

Hi Kevin,

Kevin Peng said:

As we know OSPI is backward compatible with QSPI shown in the below guide. May I know is there any SW changes required to configure the OSPI mode QSPI like some changes needed in the DTS file? The reason to ask is that customers decide to use QSPI flash, but we only have OSPI on AM62A device.

In order to use a QSPI device with the OSPI peripheral you need to modify the device tree to only configure the pins that are needed/applicable, and also set the spi-*-bus-width to 4. The cdns,phy-mode node should be removed to avoid confusion (actually it is not even accessed by the Linux Kernel, but only by U-Boot) as it is not applicable to QSPI devices with our current drivers, the same applies to the DQS signal that comes with phy-mode.

So your device tree modification would look like this example here:

diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index 21b828ab628e..37c160658dc7 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -411,11 +411,6 @@ AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
                        AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
                        AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
                        AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
-                       AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
-                       AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
-                       AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
-                       AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
-                       AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
                >;
        };
 };
@@ -793,15 +788,14 @@ &ospi0 {
        flash@0{
                compatible = "spi-nand";
                reg = <0x0>;
-               spi-tx-bus-width = <8>;
-               spi-rx-bus-width = <8>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
                spi-max-frequency = <25000000>;
                cdns,tshsl-ns = <60>;
                cdns,tsd2d-ns = <60>;
                cdns,tchsh-ns = <60>;
                cdns,tslch-ns = <60>;
                cdns,read-delay = <2>;
-               cdns,phy-mode;

                partitions {
                        compatible = "fixed-partitions";

Note that since PHY-mode is not available for QSPI devices you'll be limited to transfer speeds of 25MHz in DDR mode / 50MHz in SDR mode. So if best-possible speed/throughput is one of your design criteria you should consider sticking to OSPI.

Regards, Andreas