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AM62A7: What is the WKUP_GTC0 default clock source frequency?

Spencer Black
Prodigy 20 points
Part Number: AM62A7
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I was wondering what the default clock source is for the WKUP_GTC0 interface? The EVM appears to route this out to an expansion header by default and I just want to make sure I am following the signal/source names correctly through the TRM.

  • The WKUP_CTRL_MMR0_WKUP_GTC_CLKSEL register is stating that MAIN_PLL2_HSDIV5_CLKOUT is most likely the default option if the register bits [2-0] = 000.
  • Chasing MAIN_PLL2_HSDIV5_CLKOUT down seems to indicate that it is generated by MAIN_PLL2_REF_CLK.
  • MAIN_PLL2_REF_CLK looks like it comes from MCU_HFOSC0 which is part of the MCU domain.
  • MCU_HFOSC0 is generated by the source connected to the MCU_OSC0_XI pin.

Figure 6-92 for reference

Questions

  • So on the EVM this appears to be the 25MHz crystal (Y1)?
  • Are there any extra clock dividers happening by the time is gets to the WKUP_GTC0 interface?

Thank You,
Spencer

  • 0
    TI__Guru 63145 points

    I suggest you use the Clock Tree function provided in the SysConfig tool referenced in the Development Tools section of the datasheet. It will show you the path of clocks through the AM62Ax device.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 20 points

    Hi Paul,

    I am more on the applications side of things so I am not quite sure what I am looking at. I can't find any reference to the WKUP_GTC interface or the PLL2_HSDIV5_CLKOUT in the online sysconfig tool in the Timers section.

    I was really hoping for a quick confirmation of what the default setting is on the EVK because we have our own custom hardware that we are trying to debug.

    Thank You,
    Spencer

  • 0 in reply to Spencer Black
    TI__Guru 63145 points

    Why do you think MAIN_PLL2_HSDIV5_CLKOUT is most likely the default option?

    The TRM register definition for WKUP_CTRL_MMR0_WKUP_GTC_CLKSEL clearly shows the default clock source is MAIN_PLL0_HSDIV6_CLKOUT. This clock source can be configured to operate at 200MHz or 250MHz. Using the clock tree tool is the best way to find the default frequency for this clock.

    I will assign this thread to our Clock Tree expert so they can answer any of your questions related to using the tool.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 20 points

    Sorry about that. I see that I missed the register is set to "1h" on reset in Figure 14-3345.

    I guess I don't quite understand where you are getting 200MHz and 250MHz from since the syscfg tool is saying that MCU_HFOSC0 is 25000000 Hz and the EVM schematic is showing the MCU_OSC0_XI/O clock source being generated by U6 (25MHz oscillator) through U7 (clock buffer).

    Note that I misread the schematic earlier and thought it was being generated by Y1

    Thanks,
    Spencer

  • 0 in reply to Spencer Black
    TI__Guru 63145 points

    The 25Mhz reference clock entering the device via MCU_OSC0 is multiplied up to 2000MHz in Main_PLL0 and the PLL's output is post divided down to 200MHz or 250MHz by the post divider HSDIV6 connected to Main_PLL0.

    Regards,
    Paul

  • +1 in reply to peaves
    TI__Expert 4480 points

    Hi Spencer,

    In your SYSCONFIG screenshot, it seems you are not using the AM6X Clock Tree software product. The default software product helps to configure the peripherals and the device settings, but does not show the clock tree diagram. To show the clock tree diagram, you can either use the direct link for the AM62Ax device found on the CLOCKTREETOOL page on TI.com, or select the AM6X Clock Tree from the Software Product dropdown menu.

    Once the Clock Tree tool is opened, you should see the following screen:

    On the sidebar, you can search for the peripherals you would like to trace, in this case, WKUP_GTC0. The tool does not allow underscores in the search bar, so typing "WKUP_GTC0" will not provide any results. Instead, typing "GTC" and expanding the "TIMER MODULES" section will allow you to select the WKUP_GTC0 view. You will then see the following view:

    In this view, you can trace the two clock inputs to WKUP_GTC0. The fclk input is sourced by the 25 MHz oscillator, which passes through the clock loss mux, PLL0 and its HSDIV6 output, and the MAIN_GTCCLK_SEL mux. This shows the default frequency on the fclk pin of WKUP_GTC0 is 250 MHz. This corresponds with the path you and Paul have found from the TRM. 

    Regards,
    Megan

  • 0 in reply to Megan Singer
    Prodigy 20 points

    Thank you. I obviously wasn't understanding that there was a different sysconfig tool for the clock tree and was using the generic sysconfig to search for the AM62Ax processor: https://dev.ti.com/sysconfig/#/start