TDA4VH-Q1: How to set C71 L2 cache

Hello,

Where in your program are you trying to call the Cache_enable() function?

Best,

Asha

We do not use the rtos system. There is only one main function, and the kinematics are calculated in this function.
Therefore, all cache operations are initialized by calling csl directly after entering the main function.
Is there still some lack of memory configuration, and is it related to the mmu configuration?

int main(void)
{
   unsigned int len = 0;
   unsigned int i = 0;
   unsigned int status = 0;
   long pre = 0;
   long last = 0;

   //Cache_startup();
   Cache_enable(0xC);
   Cache_Size size;

   Cache_getSize(&size);
   printf("INFO: size.Cache_L1Size = %d\n",size.l1dSize);
   printf("INFO: size.Cache_L1Size = %d\n",size.l1pSize);
   printf("INFO: size.Cache_L2Size = %d\n",size.l2Size);
   size.l2Size = Cache_L2Size_64K;
   Cache_setSize(&size);

   Cache_getSize(&size);
   printf("INFO: size.Cache_L1Size = %d\n",size.l1dSize);
   printf("INFO: size.Cache_L1Size = %d\n",size.l1pSize);
   printf("INFO: size.Cache_L2Size = %d\n",size.l2Size);

   svd_test_init();
   pre = clock();
   dp_svd_test_main();
   last = clock();
   printf("INFO: last - pre = %lu\n",last - pre);
   printf_diag();
   ...
   ...
   return 0;
}

I've looked at the implementation of Cache_enable(). L2 cache is configured using the Cache_setSize function. But I found that Cache_initSize.l2Size = 0; So I also set size.l2Size = Cache_L2Size_64K, and then use Cache_setSize for configuration. Looking at the information obtained from Cache_getSize, it is found that the configuration was successful, but the algorithm computation time is not reduced, so it does not seem to have worked.

#pragma DATA_SECTION(Cache_initSize, ".const:Cache_initSize");
const Cache_Size Cache_initSize = {
    Cache_L1Size_32K,  /* l1pSize */
    Cache_L1Size_32K,  /* l1dSize */
    Cache_L2Size_0K,  /* l2Size */
};

void Cache_enable(uint16_t type)
{
    Cache_Size size;

    Cache_getSize(&size);

    if (type == Cache_Type_L1D) {
        size.l1dSize = Cache_initSize.l1dSize;
        Cache_setSize(&size);
    }
    else if (type == Cache_Type_L2) {
        size.l2Size = Cache_initSize.l2Size;
        Cache_setSize(&size);
    }
}

So I'm still missing some configuration on L2 SRAM

Some documentation says that cache initialization needs to be in secure mode.

My cmd file is as follows:

-stack 0x20000
-heap 0x20000
//-e _c_int00_secure

MEMORY {
   L1D_SRAM     : origin = 0x64E00000,  len = 0x004000   //16KB
   L2_SRAM      : origin = 0x64800000,  len = 0x080000   //512KB
   EXT_MEM      : origin = 0x80000000,  len = 0x0A00000
   IPC_VRING    : origin = 0xAC000000,  len = 0x1200000  //12M
   SL2_SRAM     : origin = 0x70100000,  len = 0x700000   // MSMCSRAM 7M
   DDR_C7x_1_BOOT           ( RWIX ) : ORIGIN = 0xAA200000 , LENGTH = 0x00000400

}

#define LINK_ADD SL2_SRAM

SECTIONS
{
    .text          >  LINK_ADD
    .text:_c_int00 >  LINK_ADD ALIGN(0x200000)
    //.text:_c_int00_secure > LINK_ADD  ALIGN(0x200000)
    .stack         >  LINK_ADD
    .bss           >  LINK_ADD
    .cio           >  LINK_ADD
    .const         >  LINK_ADD
    .data          >  LINK_ADD
    .switch        >  LINK_ADD
    .sysmem        >  LINK_ADD
    .far           >  LINK_ADD
    .args          >  LINK_ADD
    .pinit         >  LINK_ADD
    .cinit         >  LINK_ADD
    //.accelerated   >  L2_SRAM
    GROUP:              >  LINK_ADD
    {
        .data.Mmu_tableArray          : type=NOINIT
        .data.Mmu_tableArraySlot      : type=NOINIT
        .data.Mmu_level1Table         : type=NOINIT
        .data.Mmu_tableArray_NS       : type=NOINIT
        .data.Mmu_tableArraySlot_NS   : type=NOINIT
        .data.Mmu_level1Table_NS      : type=NOINIT
    }
    .vecs                   > LINK_ADD  //ALIGN(0x400000)
    .secure_vecs            > LINK_ADD  //ALIGN(0x200000)
}

ENTRY POINT SYMBOL: "_c_int00"  address: 0000ac200000

When I changed the entry address to _c_int00_secure and comment out _c_int00, the loaded program couldn't find main and couldn't run.

I guess the _c_int00() function I'm using is not configured with L2 (/CCS/tools/ti-cgt-c7000/lib/src/boot.c).

The _c_int00_secure() function deinitializes L2.(csl\arch\c7x\src\boot.c)

The problem now is that when I add.text:_c_int00_secure to the cmd file, the program can't find main.(There are no errors when the program is compiled and linked). So I have no way to go into secure mode to modify the size of L2.

Hi,

Yes for C71x devices, the cache will need to be set during secure mode. Have you tried modifying the cache directly in the CSL library? See csl/arch/c7x/src/c7x_module_config.c

Can you also expand on the performance issues you are seeing? 

Best,

Asha

Hi,

  1、The svd algorithm program is loaded through CCS XDS110 and takes 180us to run.（The DSP first loads vx_app_rtos_linux_c7x_2.out through U-boot）

  2、The same svd algorithm program is directly loaded through Uboot, and the calculation time is 1120us(ln -sf dsp_svd.out  j784s4-c71_0-fw)

   Based on the above two debugging points, it is found that the size of L2 is 0 for the second direct loading, and the size of L2 is 64K for the first time.I think L2 has been initialized in the vx_app_rtos_linux_c7x_2.out program. So when I load the svd algorithm through CCS again, it runs faster.Then I started trying to configure L2 in my own program

   1、For the scale I find that they use _c_int00_secure and my cmd file uses _c_int00. So I can't go into secure mode and configure L2.

   2、So I change the entry address to _c_int00_secure and add the InitMmu() it needs to call. Then configure Cache in the function.

  Now I have a new problem. My program cannot find main after downloading it through CCS.

  Can you give me a simple hello word program which use the _c_int00_secure entry function in cmd? The program can be compiled, loaded, and run normally through CCS.Do you have any other better ideas, looking forward to your answer.

Hi,

   I didn't directly modify the CSL library. Because I found that L2 size configuration is implemented through the callback function InitMmu(). Calling Cache_enable and Cache_startup in the main function does not work.

void SvdCacheInit()
{
    Cache_Size  cacheSize;

    /* Init cache size here, since this needs to be done in secure mode */
    cacheSize.l1pSize = Cache_L1Size_32K;
    cacheSize.l1dSize = Cache_L1Size_32K;
    cacheSize.l2Size  = Cache_L2Size_128K;
    Cache_setSize(&cacheSize);
}

void InitMmu(void)
{
    g_app_tirtos_c7x_mmu_map_error = 1;
    SvdInitMmu(false);
    SvdInitMmu(true);
    SvdCacheInit();
    //printf("INFO: g_app_tirtos_c7x_mmu_map_error = %d\n",g_app_tirtos_c7x_mmu_map_error);
};

Thanks,

Hi,

Thank you for the clarifications. 

Usually the C7x initialization code (located in the CSL library) will handle the switch from secure to non-secure that occurs before reaching the main() function. Generally we do not recommend running the C7x core in secure mode while running applications. Let me investigate internally and see what the most straightforward way would be to try to edit the cache sizes from your user application. 

chen chen said:

  Now I have a new problem. My program cannot find main after downloading it through CCS.

Are you loading the program differently now then mentioned in the first two methods you mentioned to test this? Could you clarify this point? 

Best,

Asha

Hi

  I replaced the entry function.text:_c_int00 with.text:_c_int00_secure in the cmd file. Programs loaded in either way will not work properly.

Thanks,

Hi,

    I replaced the CMD file in vision_apps/platform/j784s4 /rtos/c7x_1/main.c into my program and found that I could enter safe mode and configure L2 cache. Finally, it was found that the previous problem was caused by a missing configuration in my cmd file.

   The missing configuration in my cmd file is "--ram_model".Without this option, programs using the _c_int00_secure entry will not work properly.

   So can you tell me what this property configuration does?
   I have another question. The Mmu_map function is used when initializing the mmu. I know that this function configures the properties of memory. But I'm not sure what kind of attributes attrs.attrIndx will be configured for different values.
For example, Mmu_AttrIndx_MAIR0, Mmu_AttrIndx_MAIR7, Mmu_AttrIndx_MAIR4 will make this part of the memory what attributes? Is there any documentation?

Thanks，