AM1808 has no TCM?

Zheng Zhao said:

Is it true? AM1808 just didn't implement TCM?

That is correct, no TCM on AM18x/OMAPL1x devices.

Mukul,

Then there is only 8KB RAM to use (aside from cache) for time-critical data and code?

Zheng

In terms of available on chip memory yes there is the 8KB RAM  and additionally the Shared RAM (what you have referred to as L2 RAM for AM18xx).Accesses to Shared RAM is still a noticeable amount of cycles, but is better on bursting and it is still better compared to accessing external memory (where you addiitonally have to consider refresh cycles etc)

Mukul,

What is the difference between this shared memory and DDR2?

1.    From the diagram, this 128KB RAM also goes through SCR, which in principle should cause it to be much slower than 8KB RAM. Quantitatively, cold you give access time in CPU cycles for both

a.     8KB RAM

b.    128KB RAM

on AM1808?

2.    When SCR bus is busy, does the 128KB RAM compete bus with other peripherals? If this is true, then there is theoretically no predictability for 128KB RAM, and it could not offer guaranteed constant performance for time-critical code. Is this also true?

3.    For DDR2 memory, its clock cycles is almost higher than 100MHz, and 135MHz or 162MHz are very common; AM1808 CPU cycle is only around 300MHz, and the ratio between CPU clock speed and DDR2 controller speed is as small as close to 2. Why DDR2 memory access could be as slow as between [25,100] CPU cycles [§6.4.7 Performance Impact of Cache Parameters, Bryant, Randel E. & O'Hallaron, David - 2001 draft - Computer Systems A Programmer's Perspective]? Is it due to bus competition? If bus competition increases latency to such an extent, would it affect AM1808 128KB RAM in the same manner?

Zheng

Just adding to above asked questions..

Can anyone help me on how to access the 128KB on-chip memory available ?