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AM6442: Inter-Core Reset Isolation Between Main Domain Cores ( A53 and R5F)

Tuna Girisken
Prodigy 115 points
Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hello dear expert,

My question is about inter-core reset isolation beetween MAIN domain cores (A and R).

I run Linux on the A cores of the AM6442 and an mcu application on the R cores.

However, any reset I create in the mcu application (Warm resets etc.) causes the A core to reset.

My goal at this stage is that a reset in A core does not affect R core, and a reset in R core does not A core.

Also, I know that both cores are located under MAIN domain and reset processes are executed on a domain basis.

But maybe there is a software solution you can suggest.

Best Regards, Tuna Girişken

CCS: 12.5.00007
MCU+ SDK: v09.01.00.41
SysConfig: 1.18.0
SOC: AM6442

  • 0
    TI__Mastermind 46166 points

    Hello T,

    I was on training last week and yesterday was on leave.

    I am catching up all pending issues along with by them looking at your queries, and please give me two or three days to get back to you.

    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    TI__Mastermind 46166 points

    Hello Tune Girisken,

    Tuna Girisken said:

    My goal at this stage is that a reset in A core does not affect R core, and a reset in R core does not A core.

    This is not possible. In AM64X, the MAIN domain has R5F cores and A53 cores and the MCU core has M4F cores.

    So, only the M4F core is isolated from the main domain in the isolation.

    It is not possible to isolate the Reset from R5F or A53 and only isolate the Reset from the M4F core.

    Regards,

    Anil.

  • 0
    Prodigy 115 points

    Thank you for your reply .

    I understood your all explanations.

    But as part of the project I am working on, I have to solve this problem somehow.

    I have reviewed the reset related sections of the reference manual.

    Also I debugged the reset APIs.

    I noticed that all low level registers (CTRLMMR_MCU_RST_CTRL, CTRLMMR_RST_CTRL etc.) related to reset are configured as MCU Domain and MAIN Domain.

    But is it possible to change or manipulate the configuration of these registers ?

    Maybe you can discuss this with your software team and they can provide me a patch.

    In addition, is there a reset type that will solve my problem other than MCU domain or MAIN domain warm resets ?

    Lastly, I heard that this kind of reset will come under the name “Remote Reset” in the new sdk versions.

    Best Regards, Tuna Girişken.

  • +1 in reply to Tuna Girisken
    TI__Mastermind 46166 points

    Hello Tune Girisken,

    Actually, the SOC itself does not support your expectation.

    You are expecting that the Reset is not propagated to R5F and A53 core  when Reset is triggered and this is not at all possible at SOC level .

    If SOC does not support this feature, how can we handle the registers to achieve your requirements ?

    As per SOC, the reset can be propagated through the MAIN domain and MCU domains.

    So, if we enable MCU domain isolation, then the reset is not propagated through M4F core and the same reset is propagated through the main domain if you enable isolation or not.

    Regards,
    Anil.
  • 0 in reply to Swargam Anil
    Prodigy 115 points

    Thanks for your help
    But there is an API in sciclient_pm.h which name is Sciclient_pmSetModuleRst.
    Can ı use this API for my purpose ?
    What do u think ?

    Best Regards, Tuna Girişken.

  • 0 in reply to Tuna Girisken
    TI__Mastermind 46166 points

    Hello Tune Girisken,

    Tuna Girisken said:
    Sciclient_pmSetModuleRst

    Actually, the above one can be used for Local CPU reset and not for the entire SOC Reset, which means that CPU Registers are Reset and will go default state  and,  your SOC will not boot from RBL → SBL → Application when you do Local CPU Reset. After making the Local CPU reset, then you need to take care of the application starting address to start your application. If you do this local CPU reset your MSRAM , DDR and other Registers having the previous values .

    Regards,

    Anil.