TDA4VM: SerDes Filter Coefficients

Hello TI,

I am developing a SerDes Driver (baremetal) based on TI PDK implementation and the documentation. In the TI PDK function CSL_serdesPCIeInit (in csl_serdes3_pcie.c) for the case of 100MHz without SSC reference clock the function csl_wiz16m_cs_refclk100MHz_32b_PCIe_cmn_pll_no_ssc(serdesLaneEnableParams->baseAddr) is called, which set those filter values:

void csl_wiz16m_cs_refclk100MHz_32b_PCIe_cmn_pll_no_ssc(uint32_t baseAddr)
{
    CSL_wiz16b4m4csRegs *sierra_sds_reg = (CSL_wiz16b4m4csRegs *)(uintptr_t)(baseAddr);

    CSL_FINSR(*(volatile uint32_t *)(&sierra_sds_reg->CMN_CTRL_CDBREG.CMN_PLLLC_LF_COEFF_MODE1_PREG__CMN_PLLLC_MODE_PREG),31,16,(uint32_t)0x2105);
    CSL_FINSR(*(volatile uint32_t *)(&sierra_sds_reg->CMN_CTRL_CDBREG.CMN_PLLLC_LOCK_CNTSTART_PREG__CMN_PLLLC_LF_COEFF_MODE0_PREG),15,0,(uint32_t)0x2105);
    CSL_FINSR(*(volatile uint32_t *)(&sierra_sds_reg->CMN_CTRL_CDBREG.CMN_PLLLC_BWCAL_MODE1_PREG__CMN_PLLLC_CLK0_PREG),31,16,(uint32_t)0x8A06);
    CSL_FINSR(*(volatile uint32_t *)(&sierra_sds_reg->CMN_CTRL_CDBREG.CMN_PLLLC_DSMCORR_PREG__CMN_PLLLC_BWCAL_MODE0_PREG),15,0,(uint32_t)0x8A06);
}

Why those values specifically? When I don't set any values, I can still initialize the PCIe and transmit to the FPGA, so can I let everything as default for this use case (100MHz without SSC)?

Thank you,

Marina Lenza