Watch Dog Timer issue on DM8148

Sailesh Myneni

hi,

i am currently working on watch dog timer DM 8148.

i have enabled the interface clock and the functional clock(RCOSC32/RTC DIVIDER) for the watch dog module.

The problem i am facing is that, i am able to access all the registers except the counter register(WDT_WCRR). Before writing to this register i have disabled WDT by writing stop sequence to the WDT_WSPR register as mentioned in the TRM.

And another issue is ,after the writing of start sequence to the WDT_WSPR register ,the counter value is not incrementing.

Please help me in solving these issues.

Thanks,

sailesh

over 13 years ago

0 Jiewen Wang over 13 years ago

Prodigy 250 points

I'm also working on DM8148 WDT. Basically, I want to set the WDT to 2 seconds and every 1 second I'll reload the timer counter.

Here are the steps:

disable WDT ( write 0xaaaa and 0x5555 to WSPR ),

set prescaler(WCLR),

write 2 seconds to load register(WLDR),

write 1 second to delay register(WDLY),

write 0x1234 into trigger register(WTGR) to load timer counter(WCRR),

enable both overflow and delay interrupts

enable WDT ( write 0xbbbb and 0x4444 to WSPR )

In the interrupt handler, write a different value to trigger register(WTGR) on delay interrupt or disable WDT on overflow interrupt.

Besides these, in the beginning, I did software reset to WDT and polled reset done (WDST).

And in PLL and PRCM,

set WDT0 CLKSRC (0x481C52F4) to 0x00(RTCDIVIDER OUT),

set WDTIMER_CLKCTRL (0x4818158C) to 0x02(enable)

set MPUCFG_CLKSTCTRL (0x4818141C) to 0x02(enable)

set MPU_CLKSTCTRL (0x481815DC) to 0x02(enable)

I think I did everything as it's said in section 19 of DM814x Tech Ref, however the timer counter never increments.

Here is a register dump:

0x481C7000 00 0D 2A 50 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00

0x481C7014 01 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00

0x481C7028 00 00 FB FF 00 06 FF FF 34 12 00 00 00 00 00 00 00 00 00 00

0x481C703C 00 00 00 00 00 00 00 00 00 83 FF FF 44 44 00 00 00 00 00 00

0x481C7050 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 03 00 00 00

I notice WDSC (0x481C7010) is 0x10 which I set it to 0x22 (EMUFREE and SOFTRESET). Bits 2~4 were reserved and were expected to be 0. I wonder if this register causes timer counter stall.

Does anyone know how WDT suppose to work? Any comments will be greatly appreciated.

Thanks.

Jiewen

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Hardware mod support was added to DM8148 to make WDT functional.

Can you tell me the release package that you are using?

Regards,

Parth

0 Jiewen Wang over 13 years ago in reply to Parth Saxena

Prodigy 250 points

0 Jiewen Wang over 13 years ago in reply to Jiewen Wang

Prodigy 250 points

Hi Parth,

I found this http://processors.wiki.ti.com/index.php/DM81xx_AM38xx_PSP_WDT_Support. However I'm not able to find the similar layout on my EVM or schematic. Do you some board modification instruction for the EVM I'm using?

Thank you.

Jiewen

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Jiewen,

For clarification, this hwmods is a software patch that we have added. On DM8148, you do not require any board modification.

WDT should work on DM8148 if the hwmods for it are added in software. We have added that support in our last release. Can you confirm the release package that you are using?

Regards,

Parth

0 Jiewen Wang over 13 years ago in reply to Parth Saxena

Prodigy 250 points

Hi Parth,

I'm not sure if I have the answer to your question. The background is we are not running in Linux environment. We are developing device drivers in CCS. The Gel file we are using is close to the one in psp04.01.00.05. In the WDT driver I followed the drivers\watchdog\omap-wdt.c.

Regards,

Jiewen

0 Jiewen Wang over 13 years ago in reply to Jiewen Wang

Prodigy 250 points

Just want to remind you the we are running on Beta hardware (EVM: TMDXEVM8148BTA, MS_CAT_CBB_BETA_0155, Processor: X8148X3874CYE 0CAFK6C 715 CYE).

Besides, What were the hwmods had been made exactly? Do you have any lease note or document that describes them?

Thank you.

Jiewen

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Jiewen,

The following is a code snippet for GEL file that I came across and was said to be working on DM814X. Can you cross-check if you are following the same sequence? This should be all that is needed to make WDT work.

1. To freeze the WDT counter.

WR_MEM_32(0x481C7048,0x0000AAAA ); /* Stop timer configure sequence */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

WR_MEM_32(0x481C7048,0x00005555 ); /* Stop timer configure sequence */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

Later in application code, when WDT need to be enabled again, load the new counter value (WDT_TIMER_CNT) and restart the counter.

WR_MEM_32(0x481C702c, WDT_TIMER_CNT ); /* Configure the WLDR register*/

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WLDR write pending status */

trigger = RD_MEM_32(0x481C7030);

WR_MEM_32(0x481C702c, trigger+1); /*Write into the Trigger register */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

WR_MEM_32(0x481C7048,0x0000BBBB ); /* Start timer configure sequence */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

WR_MEM_32(0x481C7048,0x00004444 ); /* Start timer configure sequence */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

Regards,

Parth

0 Sailesh Myneni over 13 years ago in reply to Parth Saxena

Prodigy 30 points

hi parth,

i have a few doubts here.

1)The WDT counter is freezed using writes to the WDT_WSPR register(0x481C7048),then what is the need to poll for write pending status of WDT_WTGR register instead of WSPR register as mentioned in the comment lines.

WR_MEM_32(0x481C7048,0x0000AAAA ); /* Stop timer configure sequence */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

WR_MEM_32(0x481C7048,0x00005555 ); /* Stop timer configure sequence */

while ((RD_MEM_32(0x481C7034))) ; /* Poll for WTGR write pending status */

2) To trigger the reload the WDT_WTGR(0x481C7030) register needs to be written a value other than the existing value.But here the new value to trigger a reload which is "trigger+1" is written to the WDT_WLDR(0x481C702c) register instead of the WDT_WTGR(0x481C7030) register .

trigger = RD_MEM_32(0x481C7030);

WR_MEM_32(0x481C702c, trigger+1); /*Write into the Trigger register */

0 Parth Saxena over 13 years ago in reply to Sailesh Myneni

TI__Intellectual 1265 points

Sailesh,

I understand your point. The comment doesn't seem to be in line with the register value. To clarify the query, I will have to find out who the author of this code snippet is. But since this sequence seems to be working for WDT on DM814X, can you try this out once and get back with your observations?

Thanks and Regards,

Parth

0 Sailesh Myneni over 13 years ago in reply to Parth Saxena

Prodigy 30 points

hi Parth,

I tried out the sequence while i was working on WDT,for confirmation i tried out the sequence once again.The WDT counter is not incrementing.

Regarding the software patch for WDT you were talking about,we are using psp04.01.00.03 version .Can you please let me know in which release was the S/W patch for WDT updated.

Thanks & Regards,

sailesh.

0 Parth Saxena over 13 years ago in reply to Sailesh Myneni

TI__Intellectual 1265 points

Sailesh,

It was included in psp04.01.00.05 release package. I recommend you to move to that release and then test WDT (if you would be using it from linux).

Regards,

Parth

0 Jiewen Wang over 13 years ago in reply to Parth Saxena

Prodigy 250 points

Hi Parth,

I've tried putting disable sequence into GEL file as you suggested. It still didn’t work. I‘ve noticed that in register WDT_WDSC, bit EMUFREE is used to control emulation mode. By default or reset, it was to 0, from the description “0” means “timer counter frozen in emulation mode”. Was this the reason that WDT_WCRR not being loaded? How do you setup WDT_WDSC? Do you even setup WDT_WDSC(issue software reset) before accessing WDT registers? I have tried setting EMUFREE to 1, didn’t help at all. When you have the WDT working on TI8148, do you have a register dump?

On the other hand, when checking the new release, it mentioned code changes for WDT support were in devices.c and omap-hwmod_T81xx_data.c. I saw you have the following a code snippet added in omap-hwmod_T81xx_data.c. Since we are not in Linux environment, can you tell me what this code is doing in term of setting up the clock? What does HWMOD_INIT_NO_RESET mean?

Thank you.

Regards,

Jiewen

+static struct omap_hwmod_addr_space ti814x_wd_timer1_addrs[] = {

+ {

+ .pa_start = 0x481C7000,

+ .pa_end = 0x481C7FFF,

+ .flags = ADDR_TYPE_RT,

+ },

+};

+static struct omap_hwmod_ocp_if ti814x_l4_slow__wd_timer1 = {

+ .master = &ti816x_l4_slow_hwmod,

+ .slave = &ti814x_wd_timer1_hwmod,

+ .clk = "wdt1_ick",

+ .addr = ti814x_wd_timer1_addrs,

+ .addr_cnt = ARRAY_SIZE(ti814x_wd_timer1_addrs),

+ .user = OCP_USER_MPU,

+};

+static struct omap_hwmod_ocp_if *ti814x_wd_timer1_slaves[] = {

+ &ti814x_l4_slow__wd_timer1,

+};

+static struct omap_hwmod ti814x_wd_timer1_hwmod = {

+ .name = "wd_timer1",

+ .main_clk = "wdt1_fck",

+ .prcm = {

+ .omap4 = {

+ .clkctrl_reg = TI81XX_CM_ALWON_WDTIMER_CLKCTRL,

+ },

+ .slaves = ti814x_wd_timer1_slaves,

+ .slaves_cnt = ARRAY_SIZE(ti814x_wd_timer1_slaves),

+ .class = &wd_timer_class,

+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_TI814X),

+ .flags = HWMOD_INIT_NO_RESET,

+};

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Jiewen,

The recommended sequence to make WDT work is as follows:

Bit	Field	Description	Value at reset			Access rights
						SecCtrlWrDisable
						0			1
			HS/B	E/T	GP	HS/B	E/T	GP	All
31	SecCtrlWrDisable	Security Control Register write disable control: 0 Þ Write in this register is allowed 1 Þ Write in this register is forbidden	0	0	0	R/ OCO	R/ OCO	R/ OCO	R
30	SecureModeInitDone	0 Þ Secure Mode initialization not done 1 Þ Secure Mode initialization done	0	0	0	R/W	R/W	R/W^[1^]	R
29:3	Reserved	Reserved for Future Use	0x0	0x0	0x0	R	R	R	R
2	KEKSwEnable	KEK Software Enable control: 0 Þ Software KEK is disabled 1 Þ Software KEK is enabled (except when GenDbgEnable = 0x7ff)	0	0	0	R/W	R/W	R	R
1	WDRegEnable	Secure watchdog registers update access control: 0 Þ Access is never allowed 1 Þ Access is allowed only in Secure Mode (any mode on GP device)	1	1	1	R/ OCO	R/ OCO	R/ OCO	R
0	WDOpDisable	Secure watchdog operation enable control: 0 Þ Watchdog timer is running 1 Þ Watchdog timer is frozen	0	1	1	R/ OCO	R/ OCO	R/ OCO	R

Software Sequence for WatchDog:

Enable Watchdog by Writing CONTROL_SEC_CTRL = 0x2 (Refer the above Table). Now the Watchdog counter start running

Reset WDT by writing WDT_WDSC|= 0x2 and check the operation status by polling WDT_WDST=0x1

To stop the Watchdog counter perform following operation

Write 0xAAAA to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]

Write 0x5555 to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]

To enable clock division, set WCLR[PRE] register and check the operation status by polling WWPS[W_PEND_WCLR]=0.

To set clock division, set WCLR[PTV] register and check the operation status by polling WWPS[W_PEND_WCLR]=0

To update the WCRR do the following steps

Write the desired value into the WLDR and check the operation status by polling WWPS[W_PEND_WLDR]=0.

Read the WTGR.

Write (WTGR read value +1) into the WTGR register and check the operation status by polling WWPS[W_PEND_WTGR]=0.

This will update the WCRR with value written in WLDR.

To start the Watchdog counter perform following operation

Write 0xBBBB to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]

Write 0x4444 to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Jiewen,

The recommended sequence to make WDT work is as follows:

Bit	Field	Description	Value at reset	Access rights
31	SecCtrlWrDisable	Security Control Register write disable control: 0 Þ Write in this register is allowed 1 Þ Write in this register is forbidden	0	0	0	R/ OCO	R/ OCO	R/ OCO	R
30	SecureModeInitDone	0 Þ Secure Mode initialization not done 1 Þ Secure Mode initialization done	0	0	0	R/W	R/W	R/W^[1^]	R
29:3	Reserved	Reserved for Future Use	0x0	0x0	0x0	R	R	R	R
2	KEKSwEnable	KEK Software Enable control: 0 Þ Software KEK is disabled 1 Þ Software KEK is enabled (except when GenDbgEnable = 0x7ff)	0	0	0	R/W	R/W	R	R
1	WDRegEnable	Secure watchdog registers update access control: 0 Þ Access is never allowed 1 Þ Access is allowed only in Secure Mode (any mode on GP device)	1	1	1	R/ OCO	R/ OCO	R/ OCO	R
0	WDOpDisable	Secure watchdog operation enable control: 0 Þ Watchdog timer is running 1 Þ Watchdog timer is frozen	0	1	1	R/ OCO	R/ OCO	R/ OCO	R

Bit

Field

Description

Value at reset

Access rights

SecCtrlWrDisable

0

1

HS/B

E/T

GP

HS/B

E/T

GP

All

31

SecCtrlWrDisable

Security Control Register write disable control:

         0 Þ Write in this register is allowed

         1 Þ Write in this register is forbidden

0

0

0

R/ OCO

R/ OCO

R/

OCO

R

30

SecureModeInitDone

         0 Þ Secure Mode initialization not done

         1 Þ Secure Mode initialization done

0

0

0

R/W

R/W

R/W^[1^]

R

29:3

Reserved

Reserved for Future Use

0x0

0x0

0x0

R

R

R

R

2

KEKSwEnable

KEK Software Enable control:

0 Þ Software KEK is disabled

1 Þ Software KEK is enabled (except when GenDbgEnable = 0x7ff)

0

0

0

R/W

R/W

R

R

1

WDRegEnable

Secure watchdog registers update access control:

0 Þ Access is never allowed

1 Þ Access is allowed only in Secure Mode (any mode on GP device)

1

1

1

R/

OCO

R/

OCO

R/ OCO

R

0

WDOpDisable

Secure watchdog operation enable control:

0 Þ Watchdog timer is running

1 Þ Watchdog timer is frozen

0

1

1

R/

OCO

R/

OCO

R/ OCO

R

  Software Sequence for WatchDog:

Enable Watchdog by Writing CONTROL_SEC_CTRL = 0x2 (Refer the above Table). Now the Watchdog counter start running

Reset WDT by writing WDT_WDSC|= 0x2 and check the operation status by polling WDT_WDST=0x1
To stop the Watchdog counter perform following operation

Write 0xAAAA to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]
Write 0x5555 to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]

To enable clock division, set WCLR[PRE] register and check the operation status by polling WWPS[W_PEND_WCLR]=0.
To set clock division, set WCLR[PTV] register and check the operation status by polling WWPS[W_PEND_WCLR]=0
To update the WCRR do the following steps

Write the desired value into the WLDR and check the operation status by polling WWPS[W_PEND_WLDR]=0.
Read the WTGR.
Write (WTGR read value +1) into the WTGR register and check the operation status by polling WWPS[W_PEND_WTGR]=0.
This will update the WCRR with value written in WLDR.

To start the Watchdog counter perform following operation

Write 0xBBBB to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]
Write 0x4444 to WDT_WSPR. Poll for zero WWPS[W_PEND_WSPR]

The code snippet (hwmods) for WDT are basically hooking up the WDT module by providing information on the base address, interface clock (wdt1_ick) and functional clock (wdt1_fck). The structures that you see are setting up the appropriate clocks for WDT to function.

HWMOD_INIT_NO_RESET means to not reset this module at boot. A timer was rebooting the board infinitely. By adding this flag, the infinite reset issue got resolved.

Thanks and Regards,

Parth

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Jiewen,

The recommended sequence to make WDT work is as follows:

Bit	Field	Description	Value at reset	Access rights
31	SecCtrlWrDisable	Security Control Register write disable control: 0 Þ Write in this register is allowed 1 Þ Write in this register is forbidden	0	0	0	R/ OCO	R/ OCO	R/ OCO	R
30	SecureModeInitDone	0 Þ Secure Mode initialization not done 1 Þ Secure Mode initialization done	0	0	0	R/W	R/W	R/W^[1^]	R
29:3	Reserved	Reserved for Future Use	0x0	0x0	0x0	R	R	R	R
2	KEKSwEnable	KEK Software Enable control: 0 Þ Software KEK is disabled 1 Þ Software KEK is enabled (except when GenDbgEnable = 0x7ff)	0	0	0	R/W	R/W	R	R
1	WDRegEnable	Secure watchdog registers update access control: 0 Þ Access is never allowed 1 Þ Access is allowed only in Secure Mode (any mode on GP device)	1	1	1	R/ OCO	R/ OCO	R/ OCO	R
0	WDOpDisable	Secure watchdog operation enable control: 0 Þ Watchdog timer is running 1 Þ Watchdog timer is frozen	0	1	1	R/ OCO	R/ OCO	R/ OCO	R

HWMOD_INIT_NO_RESET means to not reset this module at boot. A timer was rebooting the board infinitely. By adding this flag, the infinite reset issue got resolved.

Thanks and Regards,

Parth

0 Jiewen Wang over 13 years ago in reply to Parth Saxena

Prodigy 250 points

Hi Parth,

Thank you for your reply. I still have questions:

1. What we are trying to use is the non-secure Cortex™A8 watchdog (WDT0). Do we have to use the secure watchdog (WDT1)? Does the non-secure watchdog ever work?

2. The table in you are referring, which document is it coming from? The PRCM document we had was preliminary draft 1.5, do you have a newer version? I wasn't able to find that table from any of the document I have. I don’t know which register you are talking about.

3. Most of the bits in the table are read only, how do you write to them?

Regards,

Jiewen

0 Parth Saxena over 13 years ago in reply to Jiewen Wang

TI__Intellectual 1265 points

Jiewen,

We currently support only WDT1. I don't have information on WDT0.

Regarding the register, I will look up the documents and get back to you where this information is documented. As far as I remember, I think the register is a write-once register.

Regards,

Parth

0 Jiewen Wang over 13 years ago in reply to Parth Saxena

Prodigy 250 points

Hi Parth,

I'm still waiting on you to find the document for me. I have downloaded a new version of DM814x TRM (sprugz8) which dated as 14 October 2011. I'm not able to locate the table or the register you are referring. Please help.

Thanks.

Jiewen

0 Ossian Riday over 12 years ago in reply to Jiewen Wang

Prodigy 70 points

I know this thread is old, but it would be helpful if someone at TI could provide the source of the documentation describing the CONTROL_SEC_CTRL register.

I'm using the DM8168, and I don't see this register documented in SPRUGX8B (dated March 2013). Various threads on this forum (http://e2e.ti.com/support/embedded/linux/f/354/p/136281/497867.aspx and others) and silicon revision advisory 2.1.65 http://www.ti.com/lit/er/sprz329d/sprz329d.pdf make reference to the CONTROL_SEC_CTRL register. Looking through various source file headers it would appear that this register is at address 0x48140100? Are there other registers in this same memory region that I should be aware of?

Considering all the questions surrounding the watchdog timer and the nebulous answers it is important to understand the current status of the watchdog on the DM8168 silicon.

Thanks,

Ossian

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