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J722SXH01EVM: Ethernet Boot Mode Support

VISHNUPRIYA J
Prodigy 21 points

Part Number: J722SXH01EVM

Hi Team,

I am trying to boot the J722S EVM with Ethernet Boot Mode with the SDK version 9.02.

I have made the changes in the defconfig to support the ethboot as shown below:

I have observed the below logs:



Could you please guide me for the Ethernet Boot to work.

  • 0
    Prodigy 21 points

    Ethboot defconfig changes as mentioned above:

    diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
    index 96fe237c..e70b8987 100644
    --- a/configs/j722s_evm_a53_defconfig
    +++ b/configs/j722s_evm_a53_defconfig
    @@ -23,6 +23,7 @@ CONFIG_OF_LIBFDT_OVERLAY=y
     CONFIG_DM_RESET=y
     CONFIG_SPL_MMC=y
     CONFIG_SPL_SERIAL=y
    +CONFIG_SPL_DRIVERS_MISC=y
     CONFIG_SPL_STACK_R_ADDR=0x82000000
     CONFIG_SPL_FS_FAT=y
     CONFIG_SPL_LIBDISK_SUPPORT=y
    @@ -44,11 +45,14 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
     CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
     CONFIG_SPL_DMA=y
     CONFIG_SPL_ENV_SUPPORT=y
    +CONFIG_SPL_ETH=y
     CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
     CONFIG_SPL_I2C=y
     CONFIG_SPL_DM_MAILBOX=y
     CONFIG_SPL_MTD_SUPPORT=y
     CONFIG_SPL_DM_SPI_FLASH=y
    +CONFIG_SPL_NET=y
    +CONFIG_SPL_NET_VCI_STRING="J722S U-Boot A53 SPL"
     CONFIG_SPL_POWER_DOMAIN=y
     CONFIG_SPL_RAM_SUPPORT=y
     CONFIG_SPL_RAM_DEVICE=y
    @@ -85,6 +89,7 @@ CONFIG_SPL_DM_DEVICE_REMOVE=y
     CONFIG_SPL_DM_SEQ_ALIAS=y
     CONFIG_REGMAP=y
     CONFIG_SPL_REGMAP=y
    +CONFIG_SYSCON=y
     CONFIG_SPL_SYSCON=y
     CONFIG_SPL_OF_TRANSLATE=y
     CONFIG_CLK=y
    diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
    index 9860fa8d..400ffcb1 100644
    --- a/configs/j722s_evm_r5_defconfig
    +++ b/configs/j722s_evm_r5_defconfig
    @@ -50,7 +50,12 @@ CONFIG_SPL_EARLY_BSS=y
     CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
     CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
     CONFIG_SPL_DMA=y
    +CONFIG_SPL_ENV_SUPPORT=y
    +CONFIG_SPL_ETH=y
    +CONFIG_SPL_I2C=y
     CONFIG_SPL_DM_MAILBOX=y
    +CONFIG_SPL_NET=y
    +CONFIG_SPL_NET_VCI_STRING="J722S U-Boot R5 SPL"
     CONFIG_SPL_MTD_SUPPORT=y
     CONFIG_SPL_DM_SPI_FLASH=y
     CONFIG_SPL_DM_RESET=y
    @@ -79,12 +84,14 @@ CONFIG_ENV_IS_NOWHERE=y
     CONFIG_ENV_IS_IN_MMC=y
     CONFIG_SYS_RELOC_GD_ENV_ADDR=y
     CONFIG_SYS_MMC_ENV_PART=1
    -# CONFIG_NET is not set
    +
     CONFIG_SPL_DM=y
     CONFIG_SPL_DM_DEVICE_REMOVE=y
     CONFIG_SPL_DM_SEQ_ALIAS=y
     CONFIG_REGMAP=y
     CONFIG_SPL_REGMAP=y
    +CONFIG_SYSCON=y
    +CONFIG_SPL_SYSCON=y
     CONFIG_SPL_OF_TRANSLATE=y
     CONFIG_CLK=y
     CONFIG_SPL_CLK=y
    @@ -113,6 +120,10 @@ CONFIG_SPI_FLASH_SOFT_RESET=y
     CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
     CONFIG_SPI_FLASH_SPANSION=y
     CONFIG_SPI_FLASH_S28HX_T=y
    +CONFIG_PHY_TI_DP83867=y
    +CONFIG_DM_ETH_PHY=y
    +CONFIG_TI_AM65_CPSW_NUSS=y
    +CONFIG_SPL_PHY=y
     CONFIG_PINCTRL=y
     # CONFIG_PINCTRL_GENERIC is not set
     CONFIG_SPL_PINCTRL=y

  • +1 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi,

    May I Know what you are trying to do?

    If you are expecting CPSW to be up at R5F SPL? you need to enable the clock and power from clk-data.c & dev.data.c from "u-boot/arch/arm/mach-k3/j722s/".
    But, above will not enable Ethernet Boot Mode.

    We haven't validated Ethernet Boot Mode yet. For this ROM code needs to support Ethernet functionality.
    Let me check internally and get back to you in next week.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi,

    Thanks for your response.

    We are working on the CPSW boot at R5F SPL.

    Could you please revert as soon as possible regarding the updates which needs to be taken care for the CPSW Boot.

    Regards,

    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi,

    I have requested internally to provide the updated clk-data.c & dev-data.c files with CPSW enable.

    Once I will receive the updated files, will share it with you.

    FYI,
    We have not tested/validated CPSW enable at SPL stage.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi,

    Thanks for the speedy response.

    Once the clk-data.c and dev-data.c files are available, we will validate the CPSW at SPL stage.

    Thanks,

    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi,

    Please find the updated dev-data.c & clk-data.c with CPSW enabled.

    Fullscreen 4331.dev-data.c Download 
    // SPDX-License-Identifier: GPL-2.0+
/*
 * J722S specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[0], NULL),
	[1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]),
	[2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]),
	[3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
	[3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
	[5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
	[6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
	[7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
	[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
	[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
	[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(178, &soc_lpsc_list[1]),
	PSC_DEV(179, &soc_lpsc_list[2]),
	PSC_DEV(58, &soc_lpsc_list[3]),
	PSC_DEV(161, &soc_lpsc_list[4]),
	PSC_DEV(75, &soc_lpsc_list[5]),
	PSC_DEV(36, &soc_lpsc_list[6]),
	PSC_DEV(102, &soc_lpsc_list[6]),
	PSC_DEV(146, &soc_lpsc_list[6]),
	PSC_DEV(13, &soc_lpsc_list[7]),
	PSC_DEV(166, &soc_lpsc_list[8]),
	PSC_DEV(135, &soc_lpsc_list[9]),
	PSC_DEV(170, &soc_lpsc_list[10]),
	PSC_DEV(177, &soc_lpsc_list[11]),
	PSC_DEV(55, &soc_lpsc_list[12]),
};

const struct ti_k3_pd_platdata j722s_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = ARRAY_SIZE(soc_psc_list),
	.num_pd = ARRAY_SIZE(soc_pd_list),
	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
	.num_devs = ARRAY_SIZE(soc_dev_list),
};

    Fullscreen 4331.clk-data.c Download 
    // SPDX-License-Identifier: GPL-2.0+
/*
 * J722S specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_hfosc0_clkout",
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
	"board_0_mmc1_clklb_out",
	"board_0_mmc1_clk_out",
};

static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
	"board_0_ospi0_dqs_out",
	"board_0_ospi0_lbclko_out",
};

static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	NULL,
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};

static const char * const main_timerclkn_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"clk_32k_rc_sel_out0",
	"postdiv4_16ff_main_0_hsdivout7_clk",
	"gluelogic_rcosc_clkout",
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	NULL,
	"board_0_cp_gemac_cpts0_rft_clk_out",
	"hsdiv4_16fft_main_1_hsdivout3_clk",
	"postdiv4_16ff_main_2_hsdivout6_clk",
	"cpsw_3guss_am67_main_0_cpts_genf0",
	"cpsw_3guss_am67_main_0_cpts_genf1",
	NULL,
	NULL,
	NULL,
	NULL,
};

static const char * const wkup_clkout_sel_out0_parents[] = {
	NULL,
	"gluelogic_lfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout2_clk",
	"hsdiv4_16fft_main_1_hsdivout2_clk",
	"postdiv4_16ff_main_2_hsdivout9_clk",
	"clk_32k_rc_sel_out0",
	"gluelogic_rcosc_clkout",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clkout_sel_io_out0_parents[] = {
	"wkup_clkout_sel_out0",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clksel_out0_parents[] = {
	"hsdiv3_16fft_main_15_hsdivout0_clk",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const main_usart0_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out0",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
	CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
	DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(36, 2, "main_timerclkn_sel_out0"),
	DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"),
	DEV_CLK(36, 4, "clk_32k_rc_sel_out0"),
	DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"),
	DEV_CLK(36, 6, "gluelogic_rcosc_clkout"),
	DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(36, 8, "board_0_ext_refclk1_out"),
	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
	DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
	DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(61, 9, "wkup_clksel_out0"),
	DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
	DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
	DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 54, "clkout0_ctrl_out0"),
	DEV_CLK(157, 55, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 56, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
	DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 159, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 173, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"),
	DEV_CLK(157, 175, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"),
	DEV_CLK(157, 178, "dmtimer_dmc1ms_main_0_timer_pwm"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 2, "board_0_tck_out"),
	DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata j722s_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = ARRAY_SIZE(clk_list),
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
};


    As informed earlier, we have not validated/tested CPSW at SPL stage.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi Sudheer,

    Thanks for the speedy response.

    We have added the clock and power domain files which you have shared. Still the same issue persists. We are debugging on this issue.

    Could you please help me to know any other files needs to be taken care for the CPSW Boot support.

    Regards,

    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi,

    VISHNUPRIYA J said:
    Could you please help me to know any other files needs to be taken care for the CPSW Boot support.

    If you want to boot CPSW at SPL stage you need to update the defconfig of R5F also, need to add the CPSW nodes in r5-evm.dts files.
    You can check with above changes.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi Sudheer,

    I have updated the below changes for the r5 and a53 dts entries as shown below:

    Change in the k3-j722s-evm-u-boot.dtsi

    Change in the k3-j722s-r5-evm.dts

    Changes in the a53 dts file (k3-j722s-evm.dts)

    Also I have updated in the j722s_init.c file also as shown below:

    After making those changes along with the defconfig changes and the clock and the power domain changes that have shared by you I have observed the below logs for the Ethernet Boot, where the Ethernet driver itself is not able to load.

    Could you please guide how to resolve the issue which I am debugging now.

    Regards,

    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi,

    Let me check once internally about this and update you.
    As it is not validated at TI side, and default SDK not supported this.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi Sudheer,

    Is there any updates?

    Regards,

    Vishnupriya J

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru* 77480 points

    Hi,

    Enabling CPSW at SPL is not supported from TI SDK, and no plan to enable in future as well.

    Will you use CPSW at u-boot or Linux stage? Which is supported from SDK itself.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi Sudheer,

    We are using CPSW at U-Boot stage. We were able to make some progress and the CPSW drivers are enumerated. However we are getting the below error:

    Looks like we need to update the tifs/rm yaml files in the SPL. But we are unsure of the changes. Could you please guide us on the same?

    Regards,

    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi, 

    CPSW enable at u-boot means not at SPL A72. It's is after SPL A72 actual u-boot stage. 

    There was some reference from other SOCs in TI for enabling ethernet at SPL, let us check and share you the reference on tomorrow. 

    Best regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    TI__Guru* 77480 points

    Hi,

    Please find the reference patchs for enabling Ethernet boot from other SoC (AM62).
    https://patchwork.ozlabs.org/project/uboot/list/?series=404418&state=%2A&archive=both

    Refer to above patches and make changes for J722S.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 21 points

    Hi Sudheer,

    Thanks for the reference. I will check and share the status.

    Regards,
    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    Prodigy 21 points

    Hi Sudheer,

    We updated the sources by referring to the AM62 patches provided by you. However, we are still facing the same issue.

    Could you please guide us on this?

    Regards,

    Vishnupriya J

  • 0 in reply to VISHNUPRIYA J
    TI__Guru* 77480 points

    Hi,

    Have you added all dependent nodes of CPSW into device tree? like PSIL thread map.. and other if any,

    Also, make sure that enabling of all dependent modules from defconfig.

    Best Regards,
    Sudheer