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Question on AM1808 EDMA3

Anonymous
Anonymous
Other Parts Discussed in Thread: AM1808

Hi,

 

I would like to ask a question on AM1808 EDMA3.

 

I use AB synchronized DMA transfer and tested with different ACNT-BCNT combinations to measured EDMA performance on DM6437, and have obtained a linear relationship of:

 

T(ms) = 26 + 3.35×10-3D

 

In which T is transfer time in ms, and D is data amount in kilo bytes. The graph is shown below:

 

 

My question is with the constant 26ms time. I speculate this 26ms time to be what is required to apply for bus (SCR) and hence is independent of the actual amount of data later being transferred. Therefore, after the bus time/resources has been allocated and the transfer has been initiated, the remaining time for actual transfer would be proportional to data amount, hence the linear relationship.

 On DM6437, the clock rate is as high as 600MHz, whereas AM1808 has 375/456-MHz clock rate. In addition to clock rate difference, the two processors are essentially of completely different architecture. However, EDMA3 is a peripheral that is located outside the CPU core, and should work with its own circuit which doesn't not depend on CPU operation. So the question is, what is the transfer speed of EDMA3 on AM1808?  Would the initial set up time be smaller or larger than 26ms?

 

Another question is on AM1808 EDMA3 transfer destination.

 

 

1.    Could destination be 128KB shared RAM?

2.    Could it be 8KB RAM inside the CPU core?

 

 

 

Zheng

 

 

 

  • 0
    TI__Guru* 83855 points

    Zheng Zhao said:

    Would the initial set up time be smaller or larger than 26ms?

     

    We don't have similar to the data you might have collected for DM6437, so I cannot give you a definitive answer. In general I won't expect to see exactly the same number. The EDMA3 module is the same, so its characteristics in terms of number of EDMA cycles it takes from the time it sees an event on the CC, to the time a command/request for data goes out on the TC boundary will be the same. However beyond that it will depend on other chip topology things like relationship between CPU/EDMA/External/Internal Memory clock frequency relations, pipelining within the SCRs and number of bridges between the source/destination path from where the TC needs to read the data from and write the data to etc. As you can alternatively interpret from your own data, the effects of initial latency will be less dominant once you start transfering bigger chunks per event/ per transfer request packet.  Hope this helps.

    Zheng Zhao said:
    Could destination be 128KB shared RAM?

    Yes, EDMA can read/write from Shared RAM.

    Zheng Zhao said:
    Could it be 8KB RAM inside the CPU core?

    No, EDMA does not have access to ARM RAM.

    You can deduce the information from the datasheet table 2-2. It has a column on peripheral accessibility.

    Regards

    Mukul

  • Anonymous
    0 Anonymous in reply to Mukul Bhatnagar

    Mukul,

    Thanks for explanation. I will test them when I have built my board.

     

    Zheng