TDA4VH-Q1: SRAM Usage

Arjun Sanu

Prodigy 140 points

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hello,

If the SRAMs available in the TDA4VH are not being used explicitly, are they by default get used as L3 cache?

Can you please provide details to understand this.

over 1 year ago

0 KB over 1 year ago

TI__Guru** 121021 points

Hi,

Please take a look at https://www.ti.com/lit/pdf/spradc1 and let us know of any follow up questions.

Regards,

0 Arjun Sanu over 1 year ago in reply to KB

Prodigy 140 points

Hi,

Thanks for the response.

From the documentation, I can see that only MSMC RAM can be configured as L3 Cache.
How about other ones like PSRAM and MSRAM? Can they also be configured as L3 Cache? The document doesn't mention this.

0 KB over 1 year ago in reply to Arjun Sanu

TI__Guru** 121021 points

Only the MSMC RAM can be optionally configured as L3 cache for the A72.

Regards,

0 Arjun Sanu over 1 year ago in reply to KB

Prodigy 140 points

Hi,
One additional question, By default (without doing any configuration) will MSMC be available as SRAM or L3 Cache ?

0 KB over 1 year ago in reply to Arjun Sanu

TI__Guru** 121021 points

Which SDK is being used?

0 Arjun Sanu over 1 year ago in reply to KB

Prodigy 140 points

We are currently using SDK 8.06, and will be migrating to 9.2 version in coming weeks.

0 KB over 1 year ago in reply to Arjun Sanu

TI__Guru** 121021 points

Below are some related e2e links:

SDK Linux 9.2

4.1.13. How to configure K3 MSMC memory for use as SRAM or L3 cache? — Processor SDK Linux for J784s4 Documentation

Below TISCI link can be referenced to determine system settings:

TISCI General Message API Documentation — TISCI User Guide

Regards,

Processors

Processors forum

TDA4VH-Q1: SRAM Usage