Other Parts Discussed in Thread: TDA4VH
Hello,
If the SRAMs available in the TDA4VH are not being used explicitly, are they by default get used as L3 cache?
Can you please provide details to understand this.
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Hi,
Please take a look at https://www.ti.com/lit/pdf/spradc1 and let us know of any follow up questions.
Regards,
kb
Hi,
Thanks for the response.
From the documentation, I can see that only MSMC RAM can be configured as L3 Cache.
How about other ones like PSRAM and MSRAM? Can they also be configured as L3 Cache? The document doesn't mention this.
Only the MSMC RAM can be optionally configured as L3 cache for the A72.
Regards,
kb
Below are some related e2e links:
SDK Linux 9.2
Below TISCI link can be referenced to determine system settings:
Regards,
kb