PROCESSOR-SDK-AM64X: Watchdog

/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
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 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include <drivers/watchdog.h>

/*
 * This is an empty project provided for all cores present in the device.
 * User can use this project to start their application by adding more SysConfig modules.
 *
 * This application does driver and board init and just prints the pass string on the console.
 * In case of the main core, the print is redirected to the UART console.
 * For all other cores, CCS prints are used.
 */

/*
 * watchdog
 */
/* watchdog atrributes */



void watchdog_interrupt_main(void);
void watchdogCallback(void *arg);
void Drivers_watchdogClose(void);
void Drivers_watchdogOpen(uint32_t mode);


#define CONFIG_WATCHDOG_NUM_INSTANCES (1U)
#define CONFIG_WDT0  (0U)
#define NUM_OF_ITERATIONS (10U)
#define INIT_CONFIG       0U
#define RUN_TIME_CONFIG   1U

#define CONFIG_WDT_INT_NUM (16U + CSLR_MCU_M4FSS0_CORE0_NVIC_MCU_RTI0_INTR_WWD_0)


volatile uint32_t   gWatchdogInt = 0;
uint32_t gWatchdogConfigNum = CONFIG_WATCHDOG_NUM_INSTANCES;


/* watchdog Driver handles */
Watchdog_Handle gWatchdogHandle[CONFIG_WATCHDOG_NUM_INSTANCES];

/* watchdog Driver Parameters */
Watchdog_Params gWatchdogParams[CONFIG_WATCHDOG_NUM_INSTANCES] =
{
    {
        .callbackFxn        = NULL,
        .callbackFxnArgs    = NULL,
        .resetMode          = Watchdog_RESET_OFF,
        .debugStallMode     = Watchdog_DEBUG_STALL_ON,
        .windowSize         = Watchdog_WINDOW_100_PERCENT,
        .expirationTime     = 10000,/* Here we need to configure M4F expiration Time in msec*/
    },
};



static Watchdog_HwAttrs gWatchdogHwAttrs[CONFIG_WATCHDOG_NUM_INSTANCES] =
{
    {
        .instance        = WATCHDOG_INST_ID_MCU_RTI0,
        .baseAddr        = CSL_MCU_RTI0_CFG_BASE,/*0x84880000, Here we need to convert CSL_MCU_RTI0_CFG_BASE address to local M4F Address space*/
        .wdtClkFrequency = 32552U,
    },
};
/* Watchdog objects - initialized by the driver */
Watchdog_MCB gWatchdogObjects[CONFIG_WATCHDOG_NUM_INSTANCES];

/* Watchdog driver configuration */
Watchdog_Config gWatchdogConfig[CONFIG_WATCHDOG_NUM_INSTANCES] =
{
    {
        .object = &gWatchdogObjects[CONFIG_WDT0],
        .hwAttrs = &gWatchdogHwAttrs[CONFIG_WDT0]
    },
};


void empty_main(void *args)
{
    /* Open drivers to open the UART driver for console */
    Drivers_open();
    Board_driversOpen();
    int32_t status;
    uint32_t Baseaddress;


    status = SOC_moduleClockEnable(TISCI_DEV_MCU_RTI0, 1);
    DebugP_assertNoLog(status == SystemP_SUCCESS);

    status = SOC_moduleSetClockFrequency( TISCI_DEV_MCU_RTI0,TISCI_DEV_MCU_RTI0_RTI_CLK,32552);
    DebugP_assertNoLog(status == SystemP_SUCCESS);

    Baseaddress = (uint32_t) AddrTranslateP_getLocalAddr(CSL_MCU_RTI0_CFG_BASE);
    gWatchdogHwAttrs[CONFIG_WATCHDOG_NUM_INSTANCES - 1U].baseAddr        = Baseaddress;

    DebugP_log("Watchdog interrupt Mode Test Started ...\r\n");


    //Drivers_watchdogOpen(INIT_CONFIG);
    Drivers_watchdogOpen(RUN_TIME_CONFIG);

    watchdog_interrupt_main();

}


void watchdog_interrupt_main(void)
{


    HwiP_Params             hwiPrms;
    int32_t                 status = SystemP_SUCCESS;
    static HwiP_Object       gRtiHwiObject;
    /* Register interrupt */
    HwiP_Params_init(&hwiPrms);
    hwiPrms.intNum      = CONFIG_WDT_INT_NUM ;
    hwiPrms.callback    = &watchdogCallback;


    status              = HwiP_construct(&gRtiHwiObject, &hwiPrms);
    DebugP_assert(status == SystemP_SUCCESS);


    DebugP_log("Watchdog interrupt Mode Test Started ...\r\n");

    while (gWatchdogInt < NUM_OF_ITERATIONS);

    DebugP_log("Watchdog Driver Interrupt received\r\n");

    DebugP_log("All tests have passed!!\r\n");

    Board_driversClose();

    Drivers_close();

    Drivers_watchdogClose();


}


void watchdogCallback(void *arg)
{
    if (gWatchdogInt < NUM_OF_ITERATIONS)
    {
        HwiP_clearInt(CONFIG_WDT_INT_NUM);
        Watchdog_clear(gWatchdogHandle[CONFIG_WDT0]);
        gWatchdogInt++;
    }
    return;
}


void Drivers_watchdogOpen(uint32_t mode)
{
    uint32_t instCnt;
    int32_t  status = SystemP_SUCCESS;

    for(instCnt = 0U; instCnt < CONFIG_WATCHDOG_NUM_INSTANCES; instCnt++)
    {
        gWatchdogHandle[instCnt] = NULL;   /* Init to NULL so that we can exit gracefully */
    }

    /* Open all instances */
    for(instCnt = 0U; instCnt < CONFIG_WATCHDOG_NUM_INSTANCES; instCnt++)
    {
        if(mode == INIT_CONFIG)
        {
            /* Call Watchdog_open() with Initialization timeout if mode is INIT_CONFIG*/
            gWatchdogParams[instCnt].expirationTime = 1000;
        }
        gWatchdogHandle[instCnt] = Watchdog_open(instCnt, &gWatchdogParams[instCnt]);
        if(NULL == gWatchdogHandle[instCnt])
        {
            DebugP_logError("Watchdog open failed for instance %d !!!\r\n", instCnt);
            status = SystemP_FAILURE;
            break;
        }
    }

    if(SystemP_FAILURE == status)
    {
        Drivers_watchdogClose();   /* Exit gracefully */
    }

    return;

}

void Drivers_watchdogClose(void)
{
    uint32_t instCnt;

    /* Close all instances that are open */
    for(instCnt = 0U; instCnt < CONFIG_WATCHDOG_NUM_INSTANCES; instCnt++)
    {
        if(gWatchdogHandle[instCnt] != NULL)
        {
            Watchdog_close(gWatchdogHandle[instCnt]);
            gWatchdogHandle[instCnt] = NULL;
        }
    }

    return;
}