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DDR3 Byte Lanes

Colin Hankins
Intellectual 570 points

Can I route a board with the byte lanes between the DDR3 UDIMM and C667x reversed? 

0->7

1->6

2->5

3->4

...

instead of

0->0

1->1

2->2

3->3

...

Or will this wreak havoc with the write and read leveling due to some timing dependence in the DSP memory controller? Looking at the specs for the DIMM and individual DDR3 ICs, there should not be a problem on that end. 

Thanks,

Colin

  • 0
    TI__Mastermind 42545 points

    Each byte lane should converge independently during leveling so it shouldn't make any difference if you switch the order.  Make sure that all of the associated signals for each byte lane (Data, DQSp/n, DQM)  are swapped and that all the length matching requirements for these signals are met.  As long as you calculate the proper lengths for the address and command signals when calculating the registers settings you shouldn't have a problem.