TDA4VM: After TDA4 wakes up from sleep, the CLEC interrupt unprocessed fault may occur

Hi,

Can you please provide the below:

1. Which SDK and SDK version is being used?
2. Is test being run on TI EVM?
3. Which boot flow is being used SBL vs SPL?
4. Is TI's SDL (Software Diagnostic Library), being used? 
5. Regarding hibernation / wakeup, can you please provide details on what H/W modues are being "hibernated" and then "woken up".

Thanks,

kb

Hi KB,

1.SDK8.6.

2.No.

3.SBL.

4.Used sdl libraries, such as ESM, ECC and other modules.

5.ACC sleep wake up signal source -> TC397 -> Control PMIC -> Power on and off TDA4.

Thanks

Thank you for the details.

This will take some time to look into will post response no later than Wed. May 29th.

Regards,

kb

Hi,

In reviewing above thread, some additional questions:

sui guoqing said:

Our CLEC interrupt unhandled fault detection mechanism is to poll the CLEC_EFR_k register,

Q1: What bit/bits are high in the CLEC_EFR_k register, and do these bits correspond to the listed GIC interrupts above?

sui guoqing said:

After repeated hibernation wake up tests, our functional safety has a probability of reporting CLEC interrupt unhandled fault.

Q2: Is above statement indicating that the GIC interrupts are not high on every power on/power off, and this issue is only seen intermittently?

Q3: At what point in the boot flow is the power on / power off run?  Is it always from the same point in time, after system has completed boot and is stable?

Thanks,

kb

Hi KB,

Q1: Yes, in addition to the above listed, there are other, I would like to know the above reasons.
Q2: Yes, this problem only comes up intermittently.
Q3: Yes.

Thanks.

Thanks,

Regarding Q1, could you please provide the values being seen in the CLEC_ERR_k r register.  Are they consistently the same bits, or does bit pattern change?

Q2, thanks. 

• Is there any discernible pattern between when issue occurs, and does not occur?
• How often does issue occur, on in every 100 on/off, 1 every 1000 on/off etc?

Q3 Thanks

Can you please confirm

• all cores in system are up and running, when the off is triggered? 
• Off will remove power to the TDA4VM device
• Asking as the CLEC_ERR_k bits being may have something to do with the state of the system as the off is applied.   
  • If it is a full power off/on of the device, then this line of questioning is not pertinent, and we can then focus on the on sequence.

Regards,

kb

Hi,KB

Q1:It is changing.

Q2:The probability of the problem happening is about 4/150.

Q3:It is a full power off/on of the device.

Thanks.

Thank you for response, please give us a few days to discuss/test internally.  Will respond no later than EOD June 7th.

Regards,

kb

Hi,KB

Is there any good news?

Hi,

My apologies, still have not been able to reproduce this issue on local setup.

Are there any updates you can share as to under what conditions the issue is seen / not seen?   This feels like a sequencing issue, where a H/W module is being initialized before a dependent H/W resource, and/or S/W is attempting to make use of H/W prior to it being available.

kb

Since there is no activity for more than 6 months, please let us know whether this is still a problem.

Br, Tommy