AM3352: AM3352 and TPS65910A3A1RSL

Hello Shaji,

Thank you for the query.

I am reviewing the inputs.

I need a searchable PDF schematic to be able to review the schematics.

Regards,

Sreenivasa

Hi Sreenivasa,

Can't share the complete schematic due to some nondisclosure issue, sharing the related side only in pdf form, please check

Regards,

Shaji C P  

PMIC & SITARA.pdf

Hello Shaji 

Thank you.

Please refer inputs i received from 2 device experts

Expert 1: 

Sreenivasa, the way I read it, some of their boards are drawing too much current in RTC mode, draining their battery too fast. 

 I would have them ensure that the board is not inadvertently or unexpectedly exiting RTC mode.  Are they monitoring this for the full 2 or 3 days?  What can trigger an exit from RTC mode, and are they monitoring these wakeup events?  Maybe they are missing something overnight.  And how are they measuring the 35uA?

 From the PMIC side, they would have to look for similar activity.  If I remember correctly, the PMIC would have to be in certain low power modes to enable the VRTC.  So maybe the PMIC is inadvertently exiting this state.  They would need away to monitor this over a long period of time.

Expert 2: 

I’m not sure if powering the RTC from the PMIC is the best option for battery life.  Refer to the below E2E thread that shows them alternative options for powering the AM335x RTC for minimum power consumption.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/933504/am3351-rtc-current-consumption/3451826#3451826

Regards,

Sreenivasa

Hello SelvaKumaran 

I see you have changed the priory of the thread.

Please be aware of the system level issues and limited information availability.

As we discuss i would suggest starting a new E2E thread  to reach out to the PMIC team for additional support.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks for the support, the PMIC VRTC section having a regulated out of 1.8V, it is an automatic changeover in the PMIC side, whenever power is available it will take input from power supply and upon power fail it will take input from the RTC battery input. Please see section 5.22.2.1 "Device Turn-On/Off With Rising/Falling Input Voltage" in the below link

https://www.ti.com/lit/ds/symlink/tps65910.pdf?ts=1716636776382&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS65910%253FkeyMatch%253DTPS65910A3A1RSL%2526tisearch%253Dsearch-everything%2526usecase%253DOPN

The 32 - 35uA was measured by putting an ammeter in series with coin cell battery power connected to Vbackup  pin of PMIC. Once you set and save your time in the RTC using GUI, then after that if we disconnect the main power for 5-10 minutes and restart the system then check the time, it will be wrong. There is no RTC issue with the main power.. but in battery backup mode after restarting it shows wrong RTC info..

There is challenge in moving the RTC battery power to SITARA, if we move the battery from PMIC to SITARA, the soft On/Off functionality won't work in PMIC..!

Regards,

Shaji C P

Hello Shaji 

Thank you.

Shaji P said:

Once you set and save your time in the RTC using GUI, then after that if we disconnect the main power for 5-10 minutes and restart the system then check the time, it will be wrong.

Is this issues also observed on 4 out of 10 boards.

You need to root cause the issue of RTC time change.

Is there some error in the RTC or does the RTC reset to some defaults to state defined in the software?

Regards,

Sreenivasa

Once we observe RTC reset, the system time goes to Linux build timestamp (2019). Which means the RTC received from Sitara is older than 2019.

We observed this issue with some batches of AM335 and not observed after replacing AM335 with some other batch IC.

More over the issue may come after 5min in off mode or may be after few days in off mode.

In few boards we see that a fresh cell with 3.0v drops to 2.6v within one day.

Most cases we  noticed that RTC reset occurs even if the cell voltage is above 2.9v.

Hello Shaji/Binu, 

 Can you please confirm the PMIC you are using. I expect you to use the PMIC in the figure 2.

https://www.ti.com/lit/ug/swcu093f/swcu093f.pdf

Figure 1. AM335x Power Supply Connections With TPS65910AA1 and TPS65910A3A1

Figure 2. AM335x Power Supply Connections With TPS65910A31A1

Regards,

Sreenivasa

Hello Shaji/Binu, 

Please refer below thread

(+) AM3358: VDDS_RTC powered from PMIC TPS65910A3 VRTC for SOC RTC backup - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Sreenivasa,

The part that we are using is TPS65910A3A1, I just cross verified it as per the Figure-1 and didn't see any issue, see the below image for details.

The area highlighted in green color are same and orange having difference, The I2C side and SW3 & FB3 power side which we are not using 

Regards,

Shaji C P

Hello Shaji C P

Thank you. 

I referenced another E2E and i assume you had a chance to review

You'll need to use the A31 version of the PMIC. Take a look at figure 2 of that user guide. In version A3 the VRTC supply will turn off when the other supplies also turn off. Choose A31 to keep VRTC on.

Kallikuppa Sreenivasa said:

I need a searchable PDF schematic to be able to review the schematics.

I asked for a searchable PDF and looks like you copied the pictures and generated a PDF. I will not be able to review or support with partial information. If you have some concerns sharing information, i would recommend doing a self review with the inputs provided.

I do not understand the I2C reference in your above mail, I see a external buck generating the processor RTC. 

You need to root cause the reason for the time being reset and i guess the PMIC revision could be one of the cause.

Regards,

Sreenivasa

Thanks Sreenivasa for the clarification on A3 vs A31.

We have been using TPS65910A3A1 for many years and we have thousands of boards in the market where RTC backup is working. The RTC reset issue started as customer complaint after few months of use. Moreover in recent production we have seen an increased percentage of RTC reset failure and the frequency of occurance also increased.

So wondering how does the RTC backup work sometimes and sometimes not  with TPS65910A3A1 !

Is it possible to keep RTC ON in TPS65910A3A1 (to make it behave like A31) by means of register settings ?

Hello Binu, 

Thank you. 

Please refer the below appnote for recommended implementation.

https://www.ti.com/lit/ug/swcu093f/swcu093f.pdf

Binu Mathew said:

So wondering how does the RTC backup work sometimes and sometimes not  with TPS65910A3A1 !

Please check if there was change in design, BOM, component values or component source, power down ramp timing or the board power consumption that could be due to feature enhancement etc.

Given the design familiarity, i do not have additional comments.

Binu Mathew said:

Is it possible to keep RTC ON in TPS65910A3A1 (to make it behave like A31) by means of register settings ?

I guess the PMIC team is better placed to answer the query. You might want to start a new thread with the PMIC team.

Regards,

Sreenivasa

Hello Binu, 

Binu Mathew said:

We have been using TPS65910A3A1 for many years and we have thousands of boards in the market where RTC backup is working. The RTC reset issue started as customer complaint after few months of use. Moreover in recent production we have seen an increased percentage of RTC reset failure and the frequency of occurance also increased.

You mentioned the PMIC has been used for years.

Any thoughts if customer has had this reviewed with the PMIC team or has some interactions with TI/

The below thread could provide some additional insight

(38) TPS65910: PMIC not functioning with AM3358 - Power management forum - Power management - TI E2E support forums

Regards,

Sreenivasa

Hi Sreenivasa,

Please see the attached evalkit schematic for reference, we have followed the same 

3644.am335x_gpevm_zczbaseboard_3h0002_schematic_rev1_6a.pdf

Regards,

Shaji C P

Hello Shaji C P

Thank you.

Not sure on what i need to do with the schematics.

Can you please confirm you have the U5 on your board.

I cant see U5 in the partial schematics you shared.

Regards,

Sreenivasa

Hello Shaji C P

Although you might be aware, wanted you to be aware that the data sheet or product focused application note takes precedence over the EVM schematics.

EVM schematics is not a reference design.

I did check above; and asking the same can you please confirm the PMIC implementation was reviewed by TI PMIC team.

Regards,

Sreenivasa

Hi Sreenivas,

U5 part is not in our design, the VRTC out from PMIC is directly connected to the RTC power in of SITARA.

Regards,

Shaji C P 

Hello Shaji C P

Thank you.

I guess the EVM had provision for both PMICs.

The PMIC RTC output currently is not connected and the DC/DC output seems to have been connected.

Kallikuppa Sreenivasa said:

Please check if there was change in design, BOM, component values or component source, power down ramp timing or the board power consumption that could be due to feature enhancement etc.

Please check the above  aspects on the board.

With the current configuration, as i understand there is limit to the load that can be supported and resets when the load is higher.

You might have to reduce the load.

Regards,

Sreenivasa

Hello Sreenivasa,

Is there any difference in 'RTC power consumption in OFF mode' for the different Revisions of AM335x ?

I see that the manual says 5mA and some forums mention few uA !  There are some forum references about RTC bug in certain revisions of AM335x. 

Also, this link is accessible now - http://processors.wiki.ti.com/index.php/AM335x_Power_Consumption_Summary

Can you throw some light about AM335x Revisions and probable connection to RTC reset issue ?

Hello Binu, 

Binu Mathew said:

Also, this link is accessible now - http://processors.wiki.ti.com/index.php/AM335x_Power_Consumption_Summary

I assume you meant the link is not accessible. I did a search and found the below PDF 

/cfs-file/__key/communityserver-discussions-components-files/791/AM335x-Power-Consumption-Summary-_2D00_-Texas-Instruments-Wiki.pdf

Binu Mathew said:

I see that the manual says 5mA

Please point me to the section of the data sheet (manual) that mentions 5 mA for RTC.

Regards,

Sreenivasa

Binu Mathew said:

Can you throw some light about AM335x Revisions and probable connection to RTC reset issue ?

Not sure what is your query.

Binu Mathew said:

Is there any difference in 'RTC power consumption in OFF mode' for the different Revisions of AM335x ?

Please have a look at the errata.

Binu Mathew said:

There are some forum references about RTC bug in certain revisions of AM335x. 

Please point me to the threads 

Binu Mathew said:

some forums mention few uA

This is what i would expect, please point me to the thread

Regards,

Sreenivasa

Hello Binu/Shaji,

Binu Mathew said:

Is it possible to keep RTC ON in TPS65910A3A1 (to make it behave like A31) by means of register settings ?

I believe we understand the current issue and it would help if you could check with the PMIC team on the max load the RTC rail could support with the current configurations, if they have any suggested workarounds and work to optimize the processor power.

Please optimize the caps on the supply rail.

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

Binu Mathew said:

There are some forum references about RTC bug in certain revisions of AM335x. 

e2e.ti.com/.../am335x-rtc-and-timekeeping

Kallikuppa Sreenivasa said:

Please have a look at the errata

I couldn't find any references of RTC power related changes in AM335x errata. But several forums discuss about RTC bug fixed in Revision 2.x

Hello Binu,

Thank you.

Binu Mathew said:

I couldn't find any references of RTC power related changes in AM335x errata. But several forums discuss about RTC bug fixed in Revision 2.x

Please share a couple of references. 

Regards,

Sreenivasa 

Kallikuppa Sreenivasa said:

Please point me to the section of the data sheet (manual) that mentions 5 mA for RTC.

Mentioned in this forum - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/170050/rtc-current-consumption-of-am335x

Also refer Table 5-10. Maximum Current Ratings at AM335x Power Terminals(1) of datasheet.

Kallikuppa Sreenivasa said:

Please share a couple of references.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/218439/am335x-rtc

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/293861/am335x-rtc-and-timekeeping

Kallikuppa Sreenivasa said:

In version A3 the VRTC supply will turn off when the other supplies also turn off. Choose A31 to keep VRTC on.

Is it really true that in PMIC A3, VRTC supply will turn off ?

The manual talks about Low-power mode as default in A3
(VRTC_REG.VRTC_OFFMASK = 0) and Full-power mode as default in A31 (VRTC_REG.VRTC_OFFMASK = 1).

Moreover our observation is that with A3, VRTC is basically working in off mode. But as mentioned in the first post, RTC reset is observed sporadically after some time/months.

• Also note that VRTC_REG is RW register by which this configuration can be changed. Anyhow we wil put this topic in PMU forum as well.

Hello Binu, 

Thank you.

Binu Mathew said:

In version A3 the VRTC supply will turn off when the other supplies also turn off. Choose A31 to keep VRTC on.

Is it really true that in PMIC A3, VRTC supply will turn off ?

The manual talks about Low-power mode as default in A3
(VRTC_REG.VRTC_OFFMASK = 0) and Full-power mode as default in A31 (VRTC_REG.VRTC_OFFMASK = 1).

I might have quoted from any of the E2E thread, The PMIC team could provide the right answer.

Binu Mathew said:

Moreover our observation is that with A3, VRTC is basically working in off mode. But as mentioned in the first post, RTC reset is observed sporadically after some time/months.

• Also note that VRTC_REG is RW register by which this configuration can be changed. Anyhow we wil put this topic in PMU forum as well.

As i understand, the VRTC in the above quoted mode is limited by power. I guess the reset of time customer is seeing could be due to this limitation.

The PMIC team should be able to provide more information.

Regards,

Sreenivasa

Hello Binu, 

The issue seems to be on 1.0 and can be ignored. 

I assume customer uses the latest silicon.

Binu Mathew said:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/218439/am335x-rtc

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/293861/am335x-rtc-and-timekeeping

Advisory 1.0.5

RTC: 32.768-kHZ Clock is Gating Off

Revisions Affected 1.0 Details

The RTC has a clock gating issue that stops the internal 32.768-kHz clock when the VDD_CORE voltage domain drops below the recommended operating range or the PWRONRSTn input terminal is held low. This issue has the following side effects:

• The RTC counters stop incrementing when the 32.768-kHz clock is gated. This causes the RTC to lose time while the clock is gated.

• A wakeup event applied to the EXT_WAKEUP input terminal is masked if the EXT_WAKEUP_DB_EN bit in the RTC PMIC register (0x98) is set to 1 which enables the de-bounce function for the EXT_WAKEUP input. This occurs because the 32.768-kHz clock is being used to clock the de-bounce circuit.

Workaround

Do not turn off the VDD_CORE power source or source a logic low to the PWRONRSTn input while expecting RTC to keep an accurate time. Do not enable the de-bounce circuit on the EXT_WAKEUP input if an external wakeup event needs to be detected while the 32.768-kHz clock is gated.

Regards,

Sreenivasa 

Hi All,

Checking if you made some progress or did some additional tests.

Regards,

Sreenivasa

AM335 ICs that have RTC issue have top marking as Rev B, but behaving like Revision A.

Do you have information on the date and die markings of Revison A(2.0) and B(2.1)?

Noted: Dates and die markings of Revisions are not mentioned in errata.

Hello Binu, 

Thanks. Is this  for the PMIC ?

Regards,

Sreenivasa

I m referring to AM335

Hello Binu,

Thank you.

Please refer below for the device marking

Figure 8-1. AM335x Device Nomenclature

Binu Mathew said:

AM335 ICs that have RTC issue have top marking as Rev B, but behaving like Revision A.

Please elaborate what you meant by behaving like revision A. Did customer have boards with revision A?

Binu Mathew said:

Do you have information on the date and die markings of Revison A(2.0) and B(2.1)?

I do not understand your requirement. Please elaborate.

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

Please elaborate what you meant by behaving like revision A. Did customer have boards with revision A?

AM335 ICs that reported RTC reset issue have top marking as Rev B, but it behaving like Revision A (RTC reset issue occurred). Where as other IC batches with top marking as Rev B itself does not show RTC reset issue.

Kallikuppa Sreenivasa said:

I do not understand your requirement. Please elaborate.

Since the top marking is not reliable (as mentioned above), we need to identify whether the IC batch used is Rev A or B by other means, Example from date code or from internal die marking. That is why asked for information regarding release date and die markings of Revision A(2.0) and B(2.1).

Hello Binu,

Thank you.

Binu Mathew said:

AM335 ICs that reported RTC reset issue have top marking as Rev B, but it behaving like Revision A (RTC reset issue occurred). Where as other IC batches with top marking as Rev B itself does not show RTC reset issue.

What do you mean by other ICs? Both devices you quote seems to be Rev B. 

Binu Mathew said:

AM335 ICs that reported RTC reset issue have top marking as Rev B, but it behaving like Revision A (RTC reset issue occurred).

Please point me to the document that says Rev A has RTC reset issue. Ex Errata 

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

What do you mean by other ICs? Both devices you quote seems to be Rev B. 

I didnt mention another IC, but I mentioned another batch IC (another date code).

Kallikuppa Sreenivasa said:

Please point me to the document that says Rev A has RTC reset issue. Ex Errata 

Refer Advisory 1.0.5 mentioning that RTC issue is affecting SILICON REVISION 1.0.

It would be helpful if you can answer my queries above.

Binu Mathew said:

What do you mean by other ICs? Both devices you quote seems to be Rev B. 

I didnt mention another IC, but I mentioned another batch IC (another date code).

Thank you for clarifying. FYI, i highlighted the previous note

AM335 ICs that reported RTC reset issue have top marking as Rev B, but it behaving like Revision A (RTC reset issue occurred). Where as other IC batches with top marking as Rev B itself does not show RTC reset issue.

Binu Mathew said:

Please point me to the document that says Rev A has RTC reset issue. Ex Errata 

Refer Advisory 1.0.5 mentioning that RTC issue is affecting SILICON REVISION 1.0.

Advisory 1.0.5 RTC: 32.768-kHZ Clock is Gating Off. I cant see the power consumption or reset issue mentioned if that is what you are indicating. Dose customer have the suggested fix implemented as per SR1 silicon for SR2..2.1 - this is not required?

Workaround

Do not turn off the VDD_CORE power source or source a logic low to the PWRONRSTn input while expecting RTC to keep an accurate time. Do not enable the de-bounce circuit on the EXT_WAKEUP input if an external wakeup event needs to be detected while the 32.768-kHz clock is gated.

The current silicon revision is 2.1 and i am not sure how this correlates to revision 1.0

Binu Mathew said:

Since the top marking is not reliable (as mentioned above), we need to identify whether the IC batch used is Rev A or B by other means, Example from date code or from internal die marking. That is why asked for information regarding release date and die markings of Revision A(2.0) and B(2.1).

I am not sure how you have been able to conclude the top marking is unreliable.

I do not have this information available and i am not sure on the applicability. We are trying to resolve a wrong PMIC usage through AM335x.

Please reach out to the Marketing/Business development team mentioning the issue and the required information.

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

I do not have this information available and i am not sure on the applicability. We are trying to resolve a wrong PMIC usage through AM335x.

How do you conclude that its wrong PMIC usage ?

We have thousands of products in the market without Date & Time issue with the same design (same PMIC and AM335). We have observed the Date & Time issue only with some batches (date codes) of AM335. We have also confirmed that the issue is with AM335 by interchanging AM335 from a good batch.

Our question is, why some batches of AM335 with top marking as RevB shows Date & Time reset issue, and some other batches with same top marking as RevB does not show the issue ? 

Hello Bina, 

Please go to the top of the thread and read through the thread for the details that has been discussed.

I attached below the EVM implementation 

Binu Mathew said:

I do not have this information available and i am not sure on the applicability. We are trying to resolve a wrong PMIC usage through AM335x.

How do you conclude that its wrong PMIC usage ?

Please go to the top of the thread and read through the thread for the details that has been discussed.

I attached below the EVM implementation 

I also attached the inputs from the expert.

TPS65910Ax User's Guide for AM335x Processors (Rev. F) (ti.com)

I guess the EVM had provision for both PMICs.

The PMIC RTC output currently is not connected and the DC/DC output seems to have been connected.

Kallikuppa Sreenivasa said:

Please check if there was change in design, BOM, component values or component source, power down ramp timing or the board power consumption that could be due to feature enhancement etc.

Please check the above  aspects on the board.

With the current configuration, as i understand there is limit to the load that can be supported and resets when the load is higher.

You might have to reduce the load.

Regards,

Sreenivasa

Kallikuppa Sreenivasa said:

Please check if there was change in design, BOM, component values or component source, power down ramp timing or the board power consumption that could be due to feature enhancement etc.

There is no change in design or other components.

As I mentioned, we have confirmed that the issue is with AM335 by interchanging AM335 in the same board from a good batch.

Hello Binu,

Kallikuppa Sreenivasa said:

Please check the above  aspects on the board.

With the current configuration, as i understand there is limit to the load that can be supported and resets when the load is higher.

You might have to reduce the load.

is there any difference in current observed between AM335x device batches.

Please read through the below PMIC app note on the recommended implementation 

TPS65910Ax User's Guide for AM335x Processors (Rev. F) (ti.com)

Kallikuppa Sreenivasa said:

Please reach out to the Marketing/Business development team mentioning the issue and the required information.

Please note the above. 

Regards,

Sreenivasa

Who will be able to provide information regarding release date and die markings of Revision (1.0), Revision A(2.0) and B(2.1) of AM335x ?

Hello Binu, 

Thank you.

Binu Mathew said:

Who will be able to provide information regarding release date and die markings of Revision (1.0), Revision A(2.0) and B(2.1) of AM335x ?

If i had the contact, i would have reached out for support and provided my inputs.

I also do not know if this is something we discuss or share over E2E.

Kallikuppa Sreenivasa said:

Please reach out to the Marketing/Business development team mentioning the issue and the required information.

This is the suggestion i have previously provided and have the same suggestion.

Regards,

Sreenivasa