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Hi Jasiitaa or other TI Expert.
Before, I asked a question about BIST. Pls refer to the link https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1326470/processor-sdk-j721e-bist-function?pifragment-323307=1#pifragment-323307=2
I followed your suggestion for changing the codes and rebuilted them. But, it unsuccessfully set up the BIST function. I would like to know what the status is now. Thanks
Thanks
Dengkuan
Hi Dengkuan,
Could you post details on what failures you are seeing?
Regards,
Josiitaa
Hi Josiitaa,
Pls refer to the debug information which was shown in the last post.
[2024-04-15 22:19:27.260]# RECV ASCII>
[2024-04-15 22:19:29.301]# RECV ASCII>
SBL Revision: 01.00.10.01 (Apr 12 2024 - 22:17:07)
[2024-04-15 22:19:29.580]# RECV ASCII>
TIFS ver: 9.1.2--v09.01.02 (Kool Koala)
[2024-04-15 22:19:30.904]# RECV ASCII>
Starting Sciserver..... PASSED
MCU R5F App started at 0 usecs
[2024-04-15 22:19:31.575]# RECV ASCII>
Loading BootImage
BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp1
Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#10, Entry point is 0x70014000
SBL_SlaveCoreBoot completed for Core ID#11, Entry point is 0x70016000
Loading BootImage
BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp2
[2024-04-15 22:19:32.355]# RECV ASCII>
Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#12, Entry point is 0x70018000
SBL_SlaveCoreBoot completed for Core ID#13, Entry point is 0x7001a000
SBL_SlaveCoreBoot completed for Core ID#16, Entry point C66X_0 booted
is 0x90030000
SBL_SlaveCoreBoot completed for Core ID#17, Entry point is 0x90930000C66X_1 booted
SBL_SlaveCoreBoot completed for Core ID#18, Entry poC7X_0 booted
int is 0x91a00000
Loading BootImage
BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp3
Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#0, Entry point is 0x70024000
[2024-04-15 22:19:33.741]# RECV ASCII>
MPU1_0 booted
[2024-04-15 22:19:36.868]# RECV ASCII>
Boot App: Started at 28 usec
Boot App: Total Num booted cores = 8
Boot App: Booted Core ID #10 at 33609 usecs
Boot App: Booted Core ID #11 at 34211 usecs
Boot App: Booted Core ID #12 at 129160 usecs
Boot App: Booted Core ID #13 at 129762 usecs
Boot App: Booted Core ID #16 at 130564 usecs
Boot App: Booted Core ID #17 at 131366 usecs
Boot App: Booted Core ID #18 at 131980 usecs
Boot App: Booted Core ID #0 at 138236 usecs
MCU Boot Task started at 28 usecs and finished at 151763 usecs
[2024-04-15 22:19:39.890]# RECV ASCII>
MCU2_0 booted
[2024-04-15 22:19:40.629]# RECV ASCII>
MCU2_1 booted
[2024-04-15 22:19:44.256]# RECV ASCII>
MCU3_0 booted
[2024-04-15 22:19:44.990]# RECV ASCII>
MCU3_1 booted
lateapps booted successfully
MCU2_0 reports: All tests have passed
Hi Dengkuan,
You are not seeing any BIST logs is that right? I will try to reproduce the issue, but please expect a delay in response. I am in training for the whole week.
Regards,
Josiitaa
Yes, I did not see the BIST logs. Pls give your suggestions when you are available. Thanks.
Hi Dengkuan,
I just tried integration the SDL BIST example with the PDK Boot Application on SDK 9.1 and I am able to see the BIST logs.
Please find below that patch that I used on J721E SDK 9.1:
From 3da90a52873cffe2c5322d1897cafe6dd7c5a2ad Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Wed, 22 May 2024 18:20:22 +0530
Subject: [PATCH] Integration of SDL BIST to PDK Boot Application
Signed-off-by: Josiitaa RL <j-rl@ti.com>
---
.../packages/ti/boot/sbl/build/boot_app.mk | 31 ++++++
.../boot/sbl/example/boot_app/boot_app_main.c | 94 +++++++++++++++++++
2 files changed, 125 insertions(+)
diff --git a/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/build/boot_app.mk b/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/build/boot_app.mk
index c17ccb9b..9703837b 100644
--- a/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/build/boot_app.mk
+++ b/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/build/boot_app.mk
@@ -49,6 +49,37 @@ ifeq ($(BOOTMODE), mmcsd)
COMP_LIST_COMMON += mmcsd sbl_lib_mmcsd fatfs_indp
endif
CFLAGS_LOCAL_COMMON += -DBOOT_MMCSD
+ ifeq ($(BOARD),$(filter $(BOARD), j721e_evm))
+ CFLAGS_LOCAL_COMMON += -DBIST_TASK_ENABLED
+ SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl
+ INCDIR += $(SDL_INSTALL_PATH)/
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist
+ INCDIR += $(SDL_INSTALL_PATH)/include
+ INCDIR += $(SDL_INSTALL_PATH)/src/sdl
+ INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC)
+ INCDIR += $(SDL_INSTALL_PATH)/osal
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+ INCDIR += $(SDL_INSTALL_PATH)/src/ip
+
+ # SDL Source File Paths
+ SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src
+ SRCDIR += $(SDL_INSTALL_PATH)/osal/src
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/lbist
+ SRCDIR += $(SDL_INSTALL_PATH)/src/ip/lbist/V0
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/lbist/soc/$(SOC)
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/pbist
+ SRCDIR += $(SDL_INSTALL_PATH)/src/ip/pbist/V0
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/pbist/soc/$(SOC)
+ SRCS_COMMON += osal_interface.c sdl_osal.c
+ SRCS_COMMON += bist.c bist_core_defs.c
+ SRCS_COMMON += lbist_utils.c lbist_defs.c
+ SRCS_COMMON += pbist_utils.c pbist_defs.c
+ SRCS_COMMON += sdl_lbist.c sdl_ip_lbist.c sdl_soc_lbist.c
+ SRCS_COMMON += sdl_pbist.c sdl_ip_pbist.c sdl_soc_pbist.c
+ SRCS_COMMON += power_seq.c armv8_power_utils.c
+ endif
endif
ifeq ($(BOOTMODE), ospi)
ifeq ($(BUILD_HS), yes)
diff --git a/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/example/boot_app/boot_app_main.c b/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
index 4c0c4995..67001569 100644
--- a/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
+++ b/pdk_jacinto_09_01_00_22/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
@@ -82,6 +82,15 @@
#include "boot_app_ospi.h"
#endif
+#if defined(BIST_TASK_ENABLED)
+#include "bist.h"
+#include "test/osal/osal_interface.h"
+#include "include/soc/j721e/sdlr_main_ctrl_mmr.h"
+#include "include/soc/j721e/sdlr_wkup_ctrl_mmr.h"
+#include "include/soc/j721e/sdlr_mcu_ctrl_mmr.h"
+#include "include/soc/j721e/sdlr_soc_baseaddress.h"
+#endif
+
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
@@ -91,9 +100,17 @@
/**< Task Priority Levels */
#define BOOT_TASK_PRIORITY (2)
+#if defined(BIST_TASK_ENABLED)
+#define BIST_TASK_PRIORITY (3)
+#define BIST_TASK_STACKSIZE (16U * 1024U)
+#endif
/* uncomment the following for debug logs */
// #define UART_PRINT_DEBUG
+/* define the unlock and lock values */
+#define KICK0_UNLOCK_VAL 0x68EF3490
+#define KICK1_UNLOCK_VAL 0xD172BC5A
+#define KICK_LOCK_VAL 0x00000000
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
@@ -104,6 +121,9 @@
/* Function Declarations */
/* ========================================================================== */
static void BootApp_TaskFxn(void* a0, void* a1);
+#if defined(BIST_TASK_ENABLED)
+static void BistApp_TaskFxn(void* a0, void* a1);
+#endif
static uint32_t Boot_App();
static void BootApp_AppSetup();
static int32_t BootApp_RequestStageCores(uint8_t stageNum);
@@ -125,6 +145,14 @@ static uint8_t gBootAppTaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
TaskP_Handle gbootTask;
static uint64_t gtimeBootAppStart, gtimeBootAppFinish;
+#if defined(BIST_TASK_ENABLED)
+static uint8_t gBist_TaskStack[BIST_TASK_STACKSIZE] __attribute__((aligned(32)));
+TaskP_Handle gbistTask;
+static uint64_t gtimeBistAppStart, gtimeBistAppFinish;
+/* Semaphore to indicate BIST Task completion */
+static SemaphoreP_Handle gBistTaskCompletedSem = NULL;
+#endif
+
int32_t main(void)
{
Board_initCfg boardCfg;
@@ -159,6 +187,30 @@ int32_t main(void)
OS_stop();
}
+ #if defined(BIST_TASK_ENABLED)
+ /* initializing the semaphores*/
+ SemaphoreP_Params semParams;
+ SemaphoreP_Params_init(&semParams);
+ gBistTaskCompletedSem = SemaphoreP_create(0, &semParams);
+ if(NULL == gBistTaskCompletedSem)
+ {
+ UART_printf("\n Semaphore create failed\r\n");
+ }
+
+ /* Initialize the task params */
+ TaskP_Params bistTaskParams;
+ TaskP_Params_init(&bistTaskParams);
+ bistTaskParams.priority = BIST_TASK_PRIORITY;
+ bistTaskParams.stack = gBist_TaskStack;
+ bistTaskParams.stacksize = sizeof (gBist_TaskStack);
+
+ gbistTask = TaskP_create(&BistApp_TaskFxn, &bistTaskParams);
+ if (NULL == gbistTask)
+ {
+ UART_printf("\nBist Task creation failed\r\n");
+ OS_stop();
+ }
+#endif
OS_start(); /* does not return */
return(0);
@@ -166,6 +218,10 @@ int32_t main(void)
static void BootApp_TaskFxn(void* a0, void* a1)
{
+#if defined(BIST_TASK_ENABLED)
+ /* Wait for the BIST task completion */
+ SemaphoreP_pend(gBistTaskCompletedSem, SemaphoreP_WAIT_FOREVER);
+#endif
gtimeBootAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
Boot_App();
@@ -177,6 +233,44 @@ static void BootApp_TaskFxn(void* a0, void* a1)
return;
}
+void BootApp_unlockMmrs(void){
+
+ *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL;
+ *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL;
+
+ *((uint32_t *)(SDL_MCU_CTRL_MMR0_CFG0_BASE + SDL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL;
+ *((uint32_t *)(SDL_MCU_CTRL_MMR0_CFG0_BASE + SDL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL;
+
+ *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL;
+ *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL;
+
+ return;
+}
+
+#if defined(BIST_TASK_ENABLED)
+static void BistApp_TaskFxn(void* a0, void* a1)
+{
+ /* Initialize the SDL osal */
+ SDL_TEST_osalInit();
+
+ gtimeBistAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+ /* Unlock MMRs before BISTs to enable access to LBIST registers */
+ BootApp_unlockMmrs();
+
+ bist_TaskFxn();
+
+ gtimeBistAppFinish = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+ UART_printf("\nMCU Bist Task started at %d usecs and finished at %d usecs\r\n", (uint32_t)gtimeBistAppStart, (uint32_t)gtimeBistAppFinish);
+
+ /* Post semaphore after BIST task completion so other tasks could start execution */
+ SemaphoreP_post(gBistTaskCompletedSem);
+
+ return;
+}
+#endif
+
uint32_t Boot_App()
{
uint32_t retVal;
--
2.34.1
Output Logs:
SBL Revision: 01.00.10.01 (Dec 6 2023 - 06:23:04)
TIFS ver: 9.1.2--v09.01.02 (Kool Koala)
Starting Sciserver..... PASSED
MCU R5F App started at 0 usecs
Starting PBIST failure insertion test on PBIST HWPOST MCU, index 0...
Starting PBIST failure insertion test on Main Infra PBIST, index 12...
Starting PBIST failure insertion test on MSMC PBIST, index 13...
Starting PBIST test on PBIST HWPOST MCU, index 0...
HW POST MCU Status : SDL_PBIST_POST_COMPLETED_SUCCESS
Starting PBIST test on Main Infra PBIST, index 12...
Starting PBIST test on MSMC PBIST, index 13...
HW POST MCU Status : SDL_LBIST_POST_TIMEOUT
HW POST DMSC Status : SDL_LBIST_POST_TIMEOUT
HW POST MCU Status : SDL_LBIST_POST_TIMEOUT
HW POST DMSC Status : SDL_LBIST_POST_TIMEOUT
Starting PBIST failure insertion test on Main R5F 0 PBIST, index 2...
Starting PBIST test on Main R5F 0 PBIST, index 2...
*** Boot stage 0 is complete, cores for this stage may now be loaded ***
Starting PBIST failure insertion test on Main R5F 1 PBIST, index 3...
Starting PBIST failure insertion test on C7X PBIST, index 4...
Starting PBIST failure insertion test on C6x core 0 PBIST, index 10...
Starting PBIST failure insertion test on C6x core 1 PBIST, index 11...
Starting PBIST failure insertion test on VPAC PBIST, index 6...
Starting PBIST failure insertion test on DMPAC PBIST, index 7...
Starting PBIST failure insertion test on A72 PBIST, index 5...
Starting PBIST failure insertion test on HC PBIST, index 9...
Starting PBIST failure insertion test on Encoder PBIST, index 14...
Starting PBIST failure insertion test on Decoder PBIST, index 15...
Starting PBIST test on Main R5F 1 PBIST, index 3...
Starting PBIST test on C7X PBIST, index 4...
Starting PBIST test on C6x core 0 PBIST, index 10...
Starting PBIST test on C6x core 1 PBIST, index 11...
Starting PBIST test on VPAC PBIST, index 6...
Starting PBIST test on DMPAC PBIST, index 7...
Starting PBIST test on A72 PBIST, index 5...
Starting PBIST test on HC PBIST, index 9...
Starting PBIST test on Encoder PBIST, index 14...
Starting PBIST test on Decoder PBIST, index 15...
*** Boot stage 1 is complete, cores for this stage may now be loaded ***
*** Boot stage 2 is complete, cores for this stage may now be loaded ***
==========================
BIST: Example App Summary:
==========================
BIST: Pre-boot Stage - Ran negative PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
BIST: Pre-boot Stage - Ran negative PBIST ID - PBIST_INSTANCE_MAIN_INFRA, Result = PASS
BIST: Pre-boot Stage - Ran negative PBIST ID - PBIST_INSTANCE_MSMC, Result = PASS
Pre-boot stage - Ran 3 negative PBIST total sections
BIST: Pre-boot Stage - Ran PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
BIST: Pre-boot Stage - Ran PBIST ID - PBIST_INSTANCE_MAIN_INFRA, Result = PASS
BIST: Pre-boot Stage - Ran PBIST ID - PBIST_INSTANCE_MSMC, Result = PASS
Pre-boot stage - Ran 3 PBIST total sections
BIST: Pre-boot Stage - Ran LBIST ID - LBIST_HWPOST_DMSC_INDEX, Result = LBIST_POST_COMPLETED_SUCCESS
BIST: Pre-boot Stage - Ran LBIST ID - LBIST_HWPOST_MCU_INDEX, Result = LBIST_POST_COMPLETED_SUCCESS
Pre-boot stage - Ran 2 LBIST total sections
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAIN_PULSAR_0, Result = PASS
BIST: Stage 0 - Ran 1 negative PBIST total sections
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAIN_PULSAR_0, Result = PASS
BIST: Stage 0 - Ran 1 PBIST total sections
BIST: Stage 0 - Ran LBIST ID - LBIST_MAIN_MCU0_INDEX, Result = PASS
BIST: Stage 0 - Ran 1 LBIST sections
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_MAIN_PULSAR_1, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_C7X, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_C66X_0, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_C66X_1, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_VPAC, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_A72, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_HC, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_ENCODER, Result = PASS
BIST: Stage 1 - Ran negative PBIST ID - PBIST_INSTANCE_DECODER, Result = PASS
BIST: Stage 1 - Ran 10 negative PBIST total sections
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_MAIN_PULSAR_1, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_C7X, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_C66X_0, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_C66X_1, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_VPAC, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_A72, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_HC, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_ENCODER, Result = PASS
BIST: Stage 1 - Ran PBIST ID - PBIST_INSTANCE_DECODER, Result = PASS
BIST: Stage 1 - Ran 10 PBIST total sections
BIST: Stage 1 - Ran LBIST ID - LBIST_MAIN_MCU1_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_C7X_CORE_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_VPAC_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_DMPAC_INDEX, Result = PASS
BIST: Stage 1 - Ran 4 LBIST sections
BIST: Stage 2 - Ran 0 negative PBIST total sections
BIST: Stage 2 - Ran 0 PBIST total sections
BIST: Stage 2 - Ran LBIST ID - LBIST_A72_CORE_INDEX, Result = PASS
BIST: Stage 2 - Ran 1 LBIST sections
MCU Bist Task started at 29 usecs and finished at 183443 usecs
Loading BootImage
BootApp_MMCBootImageLate: fp 0x 0x41c16300, fileName is 0:/lateapp1
Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#10, Entry point is 0x70014000
SBL_SlaveCoreBoot completed for Core ID#11, Entry point is 0x70016000
Loading BootImage
BootApp_MMCBootImageLate: fp 0x 0x41c16300, fileName is 0:/lateapp2
Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#12, Entry point is 0x70018000
SBL_SlaveCoreBoot completed for Core ID#13, Entry point is 0x7001a000
SBL_SlaveCoreBoot completed for Core ID#16, Entry point C66X_0 booted
is 0x90030000
SBL_SlaveCoreBoot completed for Core ID#17, Entry point is 0x90930000C66X_1 booted
SBL_SlaveCoreBoot completed for Core ID#18, Entry poC7X_0 booted
int is 0x91a00000
Loading BootImage
BootApp_MMCBootImageLate: fp 0x 0x41c16300, fileName is 0:/lateapp3
Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
SBL_SlaveCoreBoot completed for Core ID#0, Entry point is 0x70024000
MPU1_0 booted
Boot App: Started at 183836 usec
Boot App: Total Num booted cores = 8
Boot App: Booted Core ID #10 at 217514 usecs
Boot App: Booted Core ID #11 at 218121 usecs
Boot App: Booted Core ID #12 at 326155 usecs
Boot App: Booted Core ID #13 at 326761 usecs
Boot App: Booted Core ID #16 at 327573 usecs
Boot App: Booted Core ID #17 at 328384 usecs
Boot App: Booted Core ID #18 at 329003 usecs
Boot App: Booted Core ID #0 at 336065 usecs
MCU Boot Task started at 183836 usecs and finished at 349713 usecs
MCU2_0 booted
MCU2_1 booted
MCU3_0 booted
MCU3_1 booted
lateapps booted successfully
MCU2_0 reports: All tests have passed
Regards,
Josiitaa
Hi Josiitaa,
Thanks for your quick feedback. In addition, I would like to confirm whether only to add the patch into the SDK 9.1 from TI Website without other changes.
Why to ask this? Because you sent another patch to me in https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1326470/processor-sdk-j721e-bist-function?pifragment-323307=1#pifragment-323307=2, I need to confirm whether to include this. I also attach the last patch to here. Pls help to confirm this. Thanks
Dengkuan
From 8041d4a6bbc8f7ca983fce247562faa8c90df577 Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Thu, 25 Jan 2024 14:01:26 +0530
Subject: [PATCH] SDL Changes to integrate to BootApp
---
examples/bist/bist.c | 78 ++++++++++++++++++++++++++-
examples/bist/pbist_utils.c | 9 ++--
examples/bist/soc/j784s4/pbist_defs.c | 16 +++++-
3 files changed, 95 insertions(+), 8 deletions(-)
diff --git a/examples/bist/bist.c b/examples/bist/bist.c
index 09a9b43..ef89c66 100644
--- a/examples/bist/bist.c
+++ b/examples/bist/bist.c
@@ -87,7 +87,7 @@
/* ========================================================================== */
/* This flag adds more verbose prints */
-//#define DEBUG
+/*#define DEBUG*/
/* This flags enables gathering timing information for BIST stages */
#define GATHER_BIST_STAGE_DETAILS
@@ -295,6 +295,31 @@ void bist_TaskFxn(void)
{
continue;
}
+ /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */
+ if((i==7)|| (i==2)||(i==6)||(i==25))
+ {
+ continue;
+ }
+ /* HC has MMCSD in Auxiallary list, run this in SBL */
+ if(i==9)
+ {
+ continue;
+ }
+ /* TODO: Codecs are impacting QNX SDMMC driver */
+ if ((i==12) || (i==1))
+ {
+ continue;
+ }
+ /* TODO: DSS is impacting QNX SDMMC driver */
+ if (i==4)
+ {
+ continue;
+ }
+ /* TODO: Debugging issue with A72s PBIST, do not run */
+ if ((i==13)|| (i==14)||(i==15)||(i==16))
+ {
+ continue;
+ }
#endif
/*MCU instances are not supported for neg and pos test,
So skipped according to the pbist_first_boot_stage array sequence */
@@ -350,6 +375,31 @@ void bist_TaskFxn(void)
{
continue;
}
+ /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */
+ if((i==7)|| (i==2)||(i==6)||(i==25))
+ {
+ continue;
+ }
+ /* HC has MMCSD in Auxiallary list, run this in SBL */
+ if(i==9)
+ {
+ continue;
+ }
+ /* TODO: Codecs are impacting QNX SDMMC driver */
+ if ((i==12) || (i==1))
+ {
+ continue;
+ }
+ /* TODO: DSS is impacting QNX SDMMC driver */
+ if (i==4)
+ {
+ continue;
+ }
+ /* TODO: Debugging issue with A72s PBIST, do not run */
+ if ((i==13)|| (i==14)||(i==15)||(i==16))
+ {
+ continue;
+ }
#endif
/*MCU instances are not supported for neg and pos test,
So skipped according to the pbist_first_boot_stage array sequence */
@@ -395,6 +445,32 @@ void bist_TaskFxn(void)
#if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)
for (i = 0; i < num_pbists_per_boot_stage[j]; i++)
{
+
+ /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */
+ if((i==7)|| (i==2)||(i==6)||(i==25))
+ {
+ continue;
+ }
+ /* HC has MMCSD in Auxiallary list, run this in SBL */
+ if(i==9)
+ {
+ continue;
+ }
+ /* TODO: Codecs are impacting QNX SDMMC driver */
+ if ((i==12) || (i==1))
+ {
+ continue;
+ }
+ /* TODO: DSS is impacting QNX SDMMC driver */
+ if (i==4)
+ {
+ continue;
+ }
+ /* TODO: Debugging issue with A72s PBIST, do not run */
+ if ((i==13)|| (i==14)||(i==15)||(i==16))
+ {
+ continue;
+ }
/* Run test on selected instance */
testResult = PBIST_runTest(pbist_array[i], (uint8_t)PBIST_TEST_ROM);
diff --git a/examples/bist/pbist_utils.c b/examples/bist/pbist_utils.c
index ea8e5e1..f5e81da 100644
--- a/examples/bist/pbist_utils.c
+++ b/examples/bist/pbist_utils.c
@@ -535,14 +535,13 @@ int32_t PBIST_commonInit(void)
{
#if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4)
CSL_ErrType_t status;
- int32_t retValue = 0;
+
/* Add firewall entry to gain access to CLEC registers */
status = PBIST_setFirewall();
if (status != CSL_PASS)
{
UART_printf( " PBIST_setFirewall failed \n");
- retValue = -1;
}
return status;
@@ -1384,7 +1383,7 @@ int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
UART_printf(" Secondary core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
- status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecProcId,
+ status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
@@ -1403,7 +1402,7 @@ int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
UART_printf(" Third core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
- status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThProcId,
+ status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
@@ -1422,7 +1421,7 @@ int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
UART_printf(" Third core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
- status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoProcId,
+ status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
diff --git a/examples/bist/soc/j784s4/pbist_defs.c b/examples/bist/soc/j784s4/pbist_defs.c
index cd08934..fbed6b1 100755
--- a/examples/bist/soc/j784s4/pbist_defs.c
+++ b/examples/bist/soc/j784s4/pbist_defs.c
@@ -103,7 +103,7 @@
#define MAIN_R5F1_NUM_AUX_DEVICES 4
-#define MAIN_INFRA1_NUM_AUX_DEVICES 6
+#define MAIN_INFRA1_NUM_AUX_DEVICES 18
#define HC_NUM_AUX_DEVICES 12
@@ -194,6 +194,18 @@ uint32_t PBIST_MainInfra1AuxDevList[MAIN_INFRA1_NUM_AUX_DEVICES] =
TISCI_DEV_MCAN3,
TISCI_DEV_MCAN4,
TISCI_DEV_MCAN5,
+ TISCI_DEV_MCAN6,
+ TISCI_DEV_MCAN7,
+ TISCI_DEV_MCAN8,
+ TISCI_DEV_MCAN9,
+ TISCI_DEV_MCAN10,
+ TISCI_DEV_MCAN11,
+ TISCI_DEV_MCAN12,
+ TISCI_DEV_MCAN13,
+ TISCI_DEV_MCAN14,
+ TISCI_DEV_MCAN15,
+ TISCI_DEV_MCAN16,
+ TISCI_DEV_MCAN17
};
uint32_t PBIST_HCAuxDevList[HC_NUM_AUX_DEVICES] =
@@ -1423,4 +1435,4 @@ void PBIST_printPostStatus(SDL_PBIST_postResult *result)
UART_printf(" HW POST MCU Status : %s\n", (PBIST_getPostStatusString(result->mcuPostStatus)) ? : "Invalid");
return;
-}
\ No newline at end of file
+}
--
2.34.1
From 7be4cdb3861a7145099c4c0be940242276eaed46 Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Thu, 25 Jan 2024 13:59:58 +0530
Subject: [PATCH] SBL Boot + PDK Boot Application
---
packages/ti/boot/sbl/board/k3/sbl_main.c | 321 +++++++++++++++++-
packages/ti/boot/sbl/build/boot_app.mk | 42 ++-
packages/ti/boot/sbl/build/sbl_img.mk | 47 +++
.../boot/sbl/example/boot_app/boot_app_main.c | 39 +++
packages/ti/boot/sbl/sbl_component.mk | 1 +
.../src/rm_pm_hal/pm/soc/j784s4/dmsc.c | 5 +
6 files changed, 448 insertions(+), 7 deletions(-)
diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c
index 82a5177..854a2bf 100755
--- a/packages/ti/boot/sbl/board/k3/sbl_main.c
+++ b/packages/ti/boot/sbl/board/k3/sbl_main.c
@@ -43,6 +43,22 @@
#include "sbl_main.h"
#include <ti/csl/cslr_gtc.h>
#include <sbl_err_trap.h>
+#if defined (SBL_ENABLE_BIST)
+#include <bist.h>
+#include <pbist_utils.h>
+#include <sdl_pbist.h>
+#include <bist_core_defs.h>
+#include <test/osal/osal_interface.h>
+#if defined(SOC_J721E)
+#include <ti/board/src/j721e_evm/include/board_utils.h>
+#elif defined(SOC_J7200)
+#include <ti/board/src/j7200_evm/include/board_utils.h>
+#elif defined(SOC_J721S2)
+#include <ti/board/src/j721s2_evm/include/board_utils.h>
+#elif defined(SOC_J784S4)
+#include <ti/board/src/j784s4_evm/include/board_utils.h>
+#endif
+#endif
/**********************************************************************
************************** Macros ************************************
@@ -65,6 +81,52 @@ volatile uint32_t *sblProfileLogIndxAddr __attribute__((section(".sbl_profile_in
volatile uint32_t *sblProfileLogOvrFlwAddr __attribute__((section(".sbl_profile_info")));
+#if defined (SBL_ENABLE_BIST)
+#define KICK0_UNLOCK (0x68EF3490U)
+#define KICK1_UNLOCK (0xD172BC5AU)
+
+#define PLL0_LOCKKEY0 (0x00680010U)
+#define PLL0_LOCKKEY1 (0x00680014U)
+#define PLL1_LOCKKEY0 (0x00681010U)
+#define PLL1_LOCKKEY1 (0x00681014U)
+#define PLL2_LOCKKEY0 (0x00682010U)
+#define PLL2_LOCKKEY1 (0x00682014U)
+#define PLL3_LOCKKEY0 (0x00683010U)
+#define PLL3_LOCKKEY1 (0x00683014U)
+#define PLL4_LOCKKEY0 (0x00684010U)
+#define PLL4_LOCKKEY1 (0x00684014U)
+#define PLL5_LOCKKEY0 (0x00685010U)
+#define PLL5_LOCKKEY1 (0x00685014U)
+#define PLL6_LOCKKEY0 (0x00686010U)
+#define PLL6_LOCKKEY1 (0x00686014U)
+#define PLL7_LOCKKEY0 (0x00687010U)
+#define PLL7_LOCKKEY1 (0x00687014U)
+#define PLL8_LOCKKEY0 (0x00688010U)
+#define PLL8_LOCKKEY1 (0x00688014U)
+#define PLL9_LOCKKEY0 (0x00689010U)
+#define PLL9_LOCKKEY1 (0x00689014U)
+#define PLL12_LOCKKEY0 (0x0068C010U)
+#define PLL12_LOCKKEY1 (0x0068C014U)
+#define PLL14_LOCKKEY0 (0x0068E010U)
+#define PLL14_LOCKKEY1 (0x0068E014U)
+#define PLL16_LOCKKEY0 (0x00690010U)
+#define PLL16_LOCKKEY1 (0x00690014U)
+#define PLL17_LOCKKEY0 (0x00691010U)
+#define PLL17_LOCKKEY1 (0x00691014U)
+#define PLL19_LOCKKEY0 (0x00693010U)
+#define PLL19_LOCKKEY1 (0x00693014U)
+#define PLL25_LOCKKEY0 (0x00699010U)
+#define PLL25_LOCKKEY1 (0x00699014U)
+#define PLL26_LOCKKEY0 (0x0069A010U)
+#define PLL26_LOCKKEY1 (0x0069A014U)
+#if defined(SOC_J784S4)
+#define PLL27_LOCKKEY0 (0x0069B010U)
+#define PLL27_LOCKKEY1 (0x0069B014U)
+#define PLL28_LOCKKEY0 (0x0069C010U)
+#define PLL28_LOCKKEY1 (0x0069C014U)
+#endif
+#endif
+
sblEntryPoint_t k3xx_evmEntry;
const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
{
@@ -245,6 +307,199 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
};
+#if defined (SBL_ENABLE_BIST)
+
+void SBL_unlockPllMmrs(void)
+{
+ HW_WR_REG32(PLL0_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL0_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL1_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL1_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL2_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL2_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL3_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL3_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL4_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL4_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL5_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL5_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL6_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL6_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL7_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL7_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL8_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL8_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL12_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL12_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL14_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL14_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL16_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL16_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL17_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL17_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL19_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL19_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL25_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL25_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL26_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL26_LOCKKEY1, KICK1_UNLOCK);
+#if defined (SOC_J784S4)
+ HW_WR_REG32(PLL27_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL27_LOCKKEY1, KICK1_UNLOCK);
+ HW_WR_REG32(PLL28_LOCKKEY0, KICK0_UNLOCK);
+ HW_WR_REG32(PLL28_LOCKKEY1, KICK1_UNLOCK);
+#endif
+}
+
+
+static void MainDomainBootSetup(void)
+{
+ int32_t retVal;
+ Sciclient_DefaultBoardCfgInfo_t boardCfgInfo;
+
+ /* Unlock PLL MMRs putting back to same state prior to reset */
+ SBL_log(SBL_LOG_MAX, "Unlocking pll mmrs ...");
+ SBL_unlockPllMmrs();
+ SBL_log(SBL_LOG_MAX, "done.\n");
+
+ Sciclient_BoardCfgPrms_t bootAppBoardCfgPrms = {
+ .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLow,
+ .boardConfigHigh = 0,
+ .boardConfigSize = boardCfgInfo.boardCfgLowSize,
+ .devGrp = DEVGRP_01
+ };
+ Sciclient_BoardCfgPrms_t bootAppBoardCfgPmPrms = {
+ .boardConfigLow = (uint32_t)NULL,
+ .boardConfigHigh = 0,
+ .boardConfigSize = 0,
+ .devGrp = DEVGRP_01
+ };
+ Sciclient_BoardCfgPrms_t bootAppBoardCfgRmPrms = {
+ .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowRm,
+ .boardConfigHigh = 0,
+ .boardConfigSize = boardCfgInfo.boardCfgLowRmSize,
+ .devGrp = DEVGRP_01
+ };
+ Sciclient_BoardCfgPrms_t bootAppBoardCfgSecPrms = {
+ .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowSec,
+ .boardConfigHigh = 0,
+ .boardConfigSize = boardCfgInfo.boardCfgLowSecSize,
+ .devGrp = DEVGRP_01
+ };
+ retVal = Sciclient_boardCfg(&bootAppBoardCfgPrms);
+ if (retVal != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_MAX,"Sciclient_boardCfg() failed.\n");
+ }
+ retVal = Sciclient_boardCfgPm(&bootAppBoardCfgPmPrms);
+ if (retVal != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgPm() failed.\n");
+ }
+ retVal = Sciclient_boardCfgRm(&bootAppBoardCfgRmPrms);
+ if (retVal != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgRm() failed.\n");
+ }
+ retVal = Sciclient_boardCfgSec(&bootAppBoardCfgSecPrms);
+ if (retVal != CSL_PASS)
+ {
+ SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgSec() failed.\n");
+ }
+ /* Init Pinmux */
+ if(Board_init(BOARD_INIT_PINMUX_CONFIG) != BOARD_SOK)
+ {
+ SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_PINMUX_CONFIG\n");
+ }
+ /* Init PLLS */
+ Board_init(BOARD_INIT_PLL_MAIN);
+
+
+ /* Init Clocks */
+ Board_initParams_t initParams;
+ Board_getInitParams(&initParams);
+ initParams.mainClkGrp = BOARD_MAIN_CLOCK_GROUP1;
+ initParams.mcuClkGrp = BOARD_MCU_CLOCK_GROUP1;
+ Board_setInitParams(&initParams);
+ if(Board_init(BOARD_INIT_MODULE_CLOCK_MAIN) != BOARD_SOK)
+ {
+ SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_MODULE_CLOCK\n");
+ }
+
+ /* Unlock CTRL MMR */
+ SBL_log(SBL_LOG_MAX, "Unlocking CTRL MMRs ...");
+ if(Board_init(BOARD_INIT_UNLOCK_MMR) != BOARD_SOK)
+ {
+ SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_UNLOCK_MMR\n");
+ }
+ SBL_log(SBL_LOG_MAX, "done.\n");
+}
+
+#endif
+
+/* Refer TISCI_MSG_SYS_RESET in TISCI user guide for more details
+ http://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/sysreset.html */
+int32_t SBL_swResetMainDomain(void)
+{
+ int32_t retVal = E_FAIL;
+
+ struct tisci_msg_sys_reset_req request;
+ struct tisci_msg_sys_reset_resp response = {0};
+
+ Sciclient_ReqPrm_t reqParam = {0};
+ Sciclient_RespPrm_t respParam = {0};
+
+ memset(&request, 0, sizeof(request));
+ request.domain = 0x2; /* 0x2 corresponds to the MAIN domain */
+
+ reqParam.messageType = (uint16_t) TISCI_MSG_SYS_RESET;
+ reqParam.flags = (uint32_t) TISCI_MSG_FLAG_AOP;
+ reqParam.pReqPayload = (const uint8_t *) &request;
+ reqParam.reqPayloadSize = (uint32_t) sizeof (request);
+ reqParam.timeout = (uint32_t) SCICLIENT_SERVICE_WAIT_FOREVER;
+ respParam.flags = (uint32_t) 0; /* Populated by the API */
+ respParam.pRespPayload = (uint8_t *) &response;
+ respParam.respPayloadSize = (uint32_t) sizeof (response);
+
+ retVal = Sciclient_service(&reqParam, &respParam);
+ if (((respParam.flags & TISCI_MSG_FLAG_ACK) == 0) || (retVal != CSL_PASS)) {
+ SBL_log(SBL_LOG_ERR,"SBL_swResetMainDomain failed, retVal = %d\n resp flag = 0x%08x\n",
+ retVal, respParam.flags);
+ }
+
+ return retVal;
+}
+
+void SBL_runPBIST(uint32_t instanceId, bool runNegTest)
+{
+ int32_t testResult = 0;
+
+
+ if(runNegTest)
+ {
+ /* Run test on provided instance */
+ testResult = PBIST_runTest(instanceId, true);
+ /* PBIST_runtTest return value (-1 = failure and 0 = pass) */
+ if ( testResult != 0)
+ {
+ SBL_log(SBL_LOG_ERR,"PBIST negative test failed for %d\n",
+ instanceId);
+ }
+ }
+ else
+ {
+ /* Run test on provided instance */
+ testResult = PBIST_runTest(instanceId, false);
+ /* PBIST_runtTest return value (-1 = failure and 0 = pass) */
+ if ( testResult != 0)
+ {
+ SBL_log(SBL_LOG_ERR,"PBIST functional test failed for %d\n",
+ instanceId);
+ }
+ }
+}
+
+volatile uint32_t loopSwResetMainDomain = 0xDEADBEEF;
int main()
{
int32_t retVal = CSL_PASS;
@@ -359,7 +614,7 @@ int main()
#if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
SBL_ADD_PROFILE_POINT;
- SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
+ SBL_log(SBL_LOG_MAX, "Initializing PLLs ...");
if (CSL_PASS != Board_init(SBL_PLL_INIT))
{
retVal = CSL_EFAIL;
@@ -384,12 +639,64 @@ int main()
#endif
#endif
SBL_ADD_PROFILE_POINT;
- if (CSL_PASS != Board_init(SBL_CLOCK_INIT))
+ if(Board_init(SBL_CLOCK_INIT) != BOARD_SOK)
+ {
+ SBL_log(SBL_LOG_ERR,"Board_init failed for SBL_CLOCK_INIT\n");
+ retVal = CSL_EFAIL;
+ }
+ SBL_log(SBL_LOG_MAX, "done.\n");
+#endif
+
+#if defined (SBL_ENABLE_BIST)
+#if 0
+ /* For debug purpose */
+ if(loopSwResetMainDomain == 0xDEADBEEF)
{
- retVal = CSL_EFAIL;
- SBL_log(SBL_LOG_ERR, "\n Failed to initialize clocks !! \n");
+ SBL_log(SBL_LOG_MAX, "Connect CCS and change loopSwResetMainDomain to 0!\n");
+ SBL_log(SBL_LOG_MAX, "After that the MAIN domain will be reset!\n");
+ }
+ while(loopSwResetMainDomain == 0xDEADBEEF);
+#endif
+
+ /* Initialize SDL Osal Layer */
+ int32_t ret = SDL_TEST_osalInit();
+ if (ret != SDL_PASS)
+ {
+ SBL_log(SBL_LOG_MAX,"Error: Init Failed\n");
}
+ /* PBIST MAININFRA_1 Negative / Positive */
+ SBL_runPBIST(PBIST_INSTANCE_MAININFRA_1, true);
+ SBL_runPBIST(PBIST_INSTANCE_MAININFRA_1, false);
+
+ /* PBIST MAININFRA_0 Negative / Positive */
+ SBL_runPBIST(PBIST_INSTANCE_MAININFRA_0, true);
+ SBL_runPBIST(PBIST_INSTANCE_MAININFRA_0, false);
+
+ /* PBIST MSMC Negative / Positive */
+ SBL_runPBIST(PBIST_INSTANCE_MSMC, true);
+ SBL_runPBIST(PBIST_INSTANCE_MSMC, false);
+
+ /* PBIST NAVSS Negative / Positive */
+ SBL_runPBIST(PBIST_INSTANCE_NAVSS, true);
+ SBL_runPBIST(PBIST_INSTANCE_NAVSS, false);
+
+ /* PBIST HC Negative / Positive */
+ SBL_runPBIST(PBIST_INSTANCE_HC, true);
+ SBL_runPBIST(PBIST_INSTANCE_HC, false);
+
+ /* PBIST CODEC1 Negative / Positive */
+ //SBL_runPBIST(PBIST_INSTANCE_CODEC_1, true);
+ //SBL_runPBIST(PBIST_INSTANCE_CODEC_1, false);
+
+ /* Reset Main Domain */
+ SBL_log(SBL_LOG_MAX, "Resetting Main Domain ...");
+ SBL_swResetMainDomain();
+ SBL_log(SBL_LOG_MAX, "done.\n");
+
+ /* Recover Main Domain */
+ SBL_log(SBL_LOG_MAX, "Recovering Main Domain ...");
+ MainDomainBootSetup();
SBL_log(SBL_LOG_MAX, "done.\n");
#endif
@@ -400,7 +707,7 @@ int main()
retVal = CSL_EFAIL;
SBL_log(SBL_LOG_ERR, "\n Failed to initialize DDR !! \n");
}
- SBL_log(SBL_LOG_MAX, "done.\n");
+ SBL_log(SBL_LOG_MAX, "done.\n");
#endif
#if defined(SBL_ENABLE_SERDES)
@@ -418,12 +725,14 @@ int main()
SBL_log(SBL_LOG_MAX, "Initializing GTC ...");
volatile uint32_t *gtcRegister = (uint32_t *) CSL_GTC0_GTC_CFG1_BASE;
*gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK;
-
+ SBL_log(SBL_LOG_MAX, "done.\n");
#if defined(SOC_J721E) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J7200)) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J784S4))
+#if !defined (SBL_ENABLE_BIST)
/* Configure external Ethernet PHY and pinmux */
SBL_ConfigureEthernet();
#endif
#endif
+#endif
#if !defined(BOOT_PERF)
SBL_log(SBL_LOG_MAX, "Copying EEPROM content to DDR ... \n");
diff --git a/packages/ti/boot/sbl/build/boot_app.mk b/packages/ti/boot/sbl/build/boot_app.mk
index c17ccb9..0cbacef 100644
--- a/packages/ti/boot/sbl/build/boot_app.mk
+++ b/packages/ti/boot/sbl/build/boot_app.mk
@@ -64,6 +64,46 @@ ifeq ($(HLOSBOOT), linux)
else ifeq ($(HLOSBOOT), qnx)
CFLAGS_LOCAL_COMMON += -DMPU1_HLOS_BOOT_ENABLED -DHLOS_BOOT_QNX_OS
endif
+ifeq ($(HLOSBOOT), linux)
+ CFLAGS_LOCAL_COMMON += -DBIST_TASK_ENABLED
+ #CFLAGS_LOCAL_COMMON +=
+
+ # SDL Include Files
+ SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl
+ INCDIR += $(SDL_INSTALL_PATH)/
+ INCDIR += $(SDL_INSTALL_PATH)/osal/
+ INCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+ INCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+ INCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)/
+ INCDIR += $(SDL_INSTALL_PATH)/src/sdl
+ INCDIR += $(SDL_INSTALL_PATH)/test/osal/
+ INCDIR += $(SDL_INSTALL_PATH)/src/ip
+ INCDIR += $(SDL_INSTALL_PATH)/include
+ INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC)
+
+ # SDL Source File Paths
+ SRCDIR += $(SDL_INSTALL_PATH)/osal/
+ SRCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+ SRCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+ SRCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+ SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src
+
+ # SDL Integration
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/osal/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_osal.$(LIBEXT)
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_ip.$(LIBEXT)
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/sdl/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_api.$(LIBEXT)
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/r5/lib/$(SOC)/r5f/$(BUILD_PROFILE)/r5f_core.$(LIBEXT)
+
+ SRCS_COMMON += osal_interface.c
+ SRCS_COMMON += bist.c bist_core_defs.c
+ SRCS_COMMON += lbist_utils.c lbist_defs.c
+ SRCS_COMMON += pbist_utils.c pbist_defs.c
+ SRCS_COMMON += power_seq.c armv8_power_utils.c
+endif
EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/boot_app/linker_r5_freertos.lds
@@ -73,4 +113,4 @@ ifeq ($(MAKERULEDIR), )
MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
export MAKERULEDIR
endif
-include $(MAKERULEDIR)/common.mk
\ No newline at end of file
+include $(MAKERULEDIR)/common.mk
diff --git a/packages/ti/boot/sbl/build/sbl_img.mk b/packages/ti/boot/sbl/build/sbl_img.mk
index 11d2d34..0e48059 100644
--- a/packages/ti/boot/sbl/build/sbl_img.mk
+++ b/packages/ti/boot/sbl/build/sbl_img.mk
@@ -111,6 +111,53 @@ else ifeq ($(BOOTMODE), xip)
SBL_CFLAGS += -DOSPI_FREQ_166
endif
COMP_LIST_COMMON += sbl_lib_cust$(HS_SUFFIX)
+else ifeq ($(BOOTMODE), mmcsd)
+ #SBL_CFLAGS = $(CUST_SBL_FLAGS)
+ # Uncomment to enable PBIST functionality in SBL
+ SBL_CFLAGS += -DSBL_ENABLE_BIST
+ SUPRESS_WARNINGS_FLAG += -Wno-unused-but-set-variable
+
+
+ COMP_LIST_COMMON += sbl_lib_$(BOOTMODE)$(HS_SUFFIX)
+
+ # SDL Include Files
+ SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl
+ INCDIR += $(SDL_INSTALL_PATH)/
+ INCDIR += $(SDL_INSTALL_PATH)/osal/
+ INCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+ INCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+ INCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)/
+ INCDIR += $(SDL_INSTALL_PATH)/test/osal/
+ INCDIR += $(SDL_INSTALL_PATH)/test/pbist/$(SOC)/
+ INCDIR += $(SDL_INSTALL_PATH)/test/pbist/pbist_sdl/
+ INCDIR += $(SDL_INSTALL_PATH)/src/sdl
+ INCDIR += $(SDL_INSTALL_PATH)/src/ip
+ INCDIR += $(SDL_INSTALL_PATH)/include
+ INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC)
+
+ # SDL Source File Paths
+ SRCDIR += $(SDL_INSTALL_PATH)/osal/
+ SRCDIR += $(SDL_INSTALL_PATH)/bist/pbist/
+ SRCDIR += $(SDL_INSTALL_PATH)/bist/lbist/
+ SRCDIR += $(SDL_INSTALL_PATH)/bist/soc/$(SOC)/
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+ SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src
+
+
+ # SDL Integration
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/osal/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_osal.$(LIBEXT)
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_ip.$(LIBEXT)
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/sdl/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_api.$(LIBEXT)
+ EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/r5/lib/$(SOC)/r5f/$(BUILD_PROFILE)/r5f_core.$(LIBEXT)
+
+ SRCS_COMMON += osal_interface.c
+ SRCS_COMMON += bist.c bist_core_defs.c
+ SRCS_COMMON += lbist_utils.c lbist_defs.c
+ SRCS_COMMON += pbist_utils.c pbist_defs.c
+ SRCS_COMMON += power_seq.c armv8_power_utils.c
else
COMP_LIST_COMMON += sbl_lib_$(BOOTMODE)$(DMA_SUFFIX)$(HLOS_SUFFIX)$(HS_SUFFIX)
endif # ifeq ($(BOOTMODE), cust)
diff --git a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
index 4c0c499..c48c109 100644
--- a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
+++ b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
@@ -81,6 +81,10 @@
#elif defined(BOOT_OSPI)
#include "boot_app_ospi.h"
#endif
+#if defined(BIST_TASK_ENABLED)
+#include "bist.h"
+#include "test/osal/osal_interface.h"
+#endif
/* ========================================================================== */
/* Macros & Typedefs */
@@ -91,6 +95,10 @@
/**< Task Priority Levels */
#define BOOT_TASK_PRIORITY (2)
+#if defined(BIST_TASK_ENABLED)
+#define BIST_TASK_PRIORITY (3)
+#define BIST_TASK_STACKSIZE (10U * 1024U)
+#endif
/* uncomment the following for debug logs */
// #define UART_PRINT_DEBUG
@@ -125,6 +133,12 @@ static uint8_t gBootAppTaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
TaskP_Handle gbootTask;
static uint64_t gtimeBootAppStart, gtimeBootAppFinish;
+#if defined(BIST_TASK_ENABLED)
+//static uint8_t Bist_TaskStack[BIST_TASK_STACKSIZE] __attribute__((aligned(32)));
+TaskP_Handle gbistTask;
+static uint64_t gtimeBistAppStart, gtimeBistAppFinish;
+#endif
+
int32_t main(void)
{
Board_initCfg boardCfg;
@@ -177,6 +191,22 @@ static void BootApp_TaskFxn(void* a0, void* a1)
return;
}
+
+#if defined(BIST_TASK_ENABLED)
+static void BistApp_TaskFxn(void* a0, void* a1)
+{
+ gtimeBistAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+ bist_TaskFxn();
+
+ gtimeBistAppFinish = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+ UART_printf("\nMCU Bist Task started at %d usecs and finished at %d usecs\r\n", (uint32_t)gtimeBistAppStart, (uint32_t)gtimeBistAppFinish);
+
+ return;
+}
+#endif
+
uint32_t Boot_App()
{
uint32_t retVal;
@@ -205,6 +235,15 @@ uint32_t Boot_App()
}
#endif
+#if defined(BIST_TASK_ENABLED)
+
+ /* Initialize the SDL osal */
+ SDL_TEST_osalInit();
+
+ /* Start the Bist Task */
+ BistApp_TaskFxn(NULL, NULL) ;
+#endif
+
/* Initialize the entry point array to 0. */
for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
(&gK3xx_evmEntry)->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk
index 2477c72..76c9a16 100644
--- a/packages/ti/boot/sbl/sbl_component.mk
+++ b/packages/ti/boot/sbl/sbl_component.mk
@@ -1350,6 +1350,7 @@ SBL_CFLAGS += -DSBL_LOG_LEVEL=2
SBL_CFLAGS += -DSBL_ENABLE_PLL
SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
SBL_CFLAGS += -DSBL_ENABLE_DDR
+SBL_CFLAGS += -DSBL_ENABLE_BIST
ifeq ($(SOC), $(filter $(SOC), j721e))
SBL_CFLAGS += -DSBL_ENABLE_SERDES
diff --git a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c
index 748a295..739399f 100644
--- a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c
+++ b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c
@@ -95,6 +95,11 @@ static s32 wait_reset_done_with_timeout(domgrp_t domain)
if (timeout == 0U) {
ret = -ETIMEDOUT;
}
+ else
+ {
+ /* Delay to allow access Main domain */
+ osal_delay(250);
+ }
return ret;
}
--
2.34.1
Hi Dengkuan,
As mentioned in the previous E2E, those patches are to integrate BIST with the PDK BootApp to the baseline SDK 9.1 on J784s4 for reference. So you do not have to apply them now.
Please find below that patch that I used on J721E SDK 9.1
These patches are for J721E, which you can directly apply on the 9.1 SDK.
Regards,
Josiitaa
Hi Josiitaa,
Good news. I followed your suggestion to integrate the patch into SDK 9.1, and, it works.
For next step, can you give some suggestions about how to build up the same function based on SDK 9.1 or SDK 9.2 for J784S4?
Also, I would like to know how to work based on SPL mode for J721E and J784S4
Thanks
Dengkuan
Hi Dengkuan,
For next step, can you give some suggestions about how to build up the same function based on SDK 9.1 or SDK 9.2 for J784S4?
The patches shared in the previous E2E are for SDK 9.1 J784S4. You can ignore the SBL related changes there. What issues are you facing there?
Also, I would like to know how to work based on SPL mode for J721E and J784S4
Could you provide more details on what the expectation here is?
Regards,
Josiitaa
Hi Josiitaa，
I copied the patches into here. You can scan my reply and check whether the patches are right. Also, I highlighted the codes which should be changed based on your suggestion. Pls help to check. Before, I changed all codes based on your suggestion in previous E2E, but I met that BIST was not stated. I also attached the test result into my reply.
The patches shared in the previous E2E are for SDK 9.1 J784S4. You can ignore the SBL related changes there. What issues are you facing there?
For the demo order of BIST function, I thought that it was quick way to integrate BIST function into SBL mode because there is an example in SDK. Actually, our system is based on SPL mode. This is why to ask the suggestion.
Also, I would like to know how to work based on SPL mode for J721E and J784S4Could you provide more details on what the expectation here is?
Thanks
Dengkuan
Hi Dengkuan,
I copied the patches into here. You can scan my reply and check whether the patches are right. Also, I highlighted the codes which should be changed based on your suggestion. Pls help to check. Before, I changed all codes based on your suggestion in previous E2E, but I met that BIST was not stated. I also attached the test result into my reply.
I will go through the patches and send out the code changes similar to what I shared for J721E by next week.
For the demo order of BIST function, I thought that it was quick way to integrate BIST function into SBL mode because there is an example in SDK. Actually, our system is based on SPL mode. This is why to ask the suggestion.
We do not support BIST on SPL. This feature is not part of the standard SDK release. SBL flow is recommended as it a standard and faster boot loader for safety.
Regards,
Josiitaa
Hi Dengkuan,
Please find below the patch for integration of BIST with SBL Boot Application on J784s4 SDK 9.1:
From 7e1fb6ed26730dcbd4304c4768c49ee43883b0da Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Mon, 27 May 2024 15:48:29 +0530
Subject: [PATCH] Integration of SDL BIST to PDK Boot Application - j784s4 SDK
9.1
Signed-off-by: Josiitaa RL <j-rl@ti.com>
---
packages/ti/boot/sbl/build/boot_app.mk | 31 +++++++
.../boot/sbl/example/boot_app/boot_app_main.c | 93 +++++++++++++++++++
2 files changed, 124 insertions(+)
diff --git a/packages/ti/boot/sbl/build/boot_app.mk b/packages/ti/boot/sbl/build/boot_app.mk
index c17ccb9b..98b86e55 100644
--- a/packages/ti/boot/sbl/build/boot_app.mk
+++ b/packages/ti/boot/sbl/build/boot_app.mk
@@ -49,6 +49,37 @@ ifeq ($(BOOTMODE), mmcsd)
COMP_LIST_COMMON += mmcsd sbl_lib_mmcsd fatfs_indp
endif
CFLAGS_LOCAL_COMMON += -DBOOT_MMCSD
+ ifeq ($(BOARD),$(filter $(BOARD), j784s4_evm))
+ CFLAGS_LOCAL_COMMON += -DBIST_TASK_ENABLED
+ SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl
+ INCDIR += $(SDL_INSTALL_PATH)/
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist
+ INCDIR += $(SDL_INSTALL_PATH)/include
+ INCDIR += $(SDL_INSTALL_PATH)/src/sdl
+ INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC)
+ INCDIR += $(SDL_INSTALL_PATH)/osal
+ INCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+ INCDIR += $(SDL_INSTALL_PATH)/src/ip
+
+ # SDL Source File Paths
+ SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src
+ SRCDIR += $(SDL_INSTALL_PATH)/osal/src
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist
+ SRCDIR += $(SDL_INSTALL_PATH)/examples/bist/soc/$(SOC)
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/lbist
+ SRCDIR += $(SDL_INSTALL_PATH)/src/ip/lbist/V0
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/lbist/soc/$(SOC)
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/pbist
+ SRCDIR += $(SDL_INSTALL_PATH)/src/ip/pbist/V0
+ SRCDIR += $(SDL_INSTALL_PATH)/src/sdl/pbist/soc/$(SOC)
+ SRCS_COMMON += osal_interface.c sdl_osal.c
+ SRCS_COMMON += bist.c bist_core_defs.c
+ SRCS_COMMON += lbist_utils.c lbist_defs.c
+ SRCS_COMMON += pbist_utils.c pbist_defs.c
+ SRCS_COMMON += sdl_lbist.c sdl_ip_lbist.c sdl_soc_lbist.c
+ SRCS_COMMON += sdl_pbist.c sdl_ip_pbist.c sdl_soc_pbist.c
+ SRCS_COMMON += power_seq.c armv8_power_utils.c
+ endif
endif
ifeq ($(BOOTMODE), ospi)
ifeq ($(BUILD_HS), yes)
diff --git a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
index 4c0c4995..b3bededb 100644
--- a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
+++ b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c
@@ -82,6 +82,15 @@
#include "boot_app_ospi.h"
#endif
+#if defined(BIST_TASK_ENABLED)
+#include "bist.h"
+#include "test/osal/osal_interface.h"
+#include "include/soc/j784s4/sdlr_main_ctrl_mmr.h"
+#include "include/soc/j784s4/sdlr_wkup_ctrl_mmr.h"
+#include "include/soc/j784s4/sdlr_mcu_ctrl_mmr.h"
+#include "include/soc/j784s4/sdlr_soc_baseaddress.h"
+#endif
+
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
@@ -91,9 +100,17 @@
/**< Task Priority Levels */
#define BOOT_TASK_PRIORITY (2)
+#if defined(BIST_TASK_ENABLED)
+#define BIST_TASK_PRIORITY (3)
+#define BIST_TASK_STACKSIZE (16U * 1024U)
+#endif
/* uncomment the following for debug logs */
// #define UART_PRINT_DEBUG
+/* define the unlock and lock values */
+#define KICK0_UNLOCK_VAL 0x68EF3490
+#define KICK1_UNLOCK_VAL 0xD172BC5A
+#define KICK_LOCK_VAL 0x00000000
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
@@ -104,6 +121,9 @@
/* Function Declarations */
/* ========================================================================== */
static void BootApp_TaskFxn(void* a0, void* a1);
+#if defined(BIST_TASK_ENABLED)
+static void BistApp_TaskFxn(void* a0, void* a1);
+#endif
static uint32_t Boot_App();
static void BootApp_AppSetup();
static int32_t BootApp_RequestStageCores(uint8_t stageNum);
@@ -125,6 +145,14 @@ static uint8_t gBootAppTaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
TaskP_Handle gbootTask;
static uint64_t gtimeBootAppStart, gtimeBootAppFinish;
+#if defined(BIST_TASK_ENABLED)
+static uint8_t gBist_TaskStack[BIST_TASK_STACKSIZE] __attribute__((aligned(32)));
+TaskP_Handle gbistTask;
+static uint64_t gtimeBistAppStart, gtimeBistAppFinish;
+/* Semaphore to indicate BIST Task completion */
+static SemaphoreP_Handle gBistTaskCompletedSem = NULL;
+#endif
+
int32_t main(void)
{
Board_initCfg boardCfg;
@@ -158,7 +186,30 @@ int32_t main(void)
UART_printf("\nBoot Task creation failed\r\n");
OS_stop();
}
+ #if defined(BIST_TASK_ENABLED)
+ /* initializing the semaphores*/
+ SemaphoreP_Params semParams;
+ SemaphoreP_Params_init(&semParams);
+ gBistTaskCompletedSem = SemaphoreP_create(0, &semParams);
+ if(NULL == gBistTaskCompletedSem)
+ {
+ UART_printf("\n Semaphore create failed\r\n");
+ }
+ /* Initialize the task params */
+ TaskP_Params bistTaskParams;
+ TaskP_Params_init(&bistTaskParams);
+ bistTaskParams.priority = BIST_TASK_PRIORITY;
+ bistTaskParams.stack = gBist_TaskStack;
+ bistTaskParams.stacksize = sizeof (gBist_TaskStack);
+
+ gbistTask = TaskP_create(&BistApp_TaskFxn, &bistTaskParams);
+ if (NULL == gbistTask)
+ {
+ UART_printf("\nBist Task creation failed\r\n");
+ OS_stop();
+ }
+#endif
OS_start(); /* does not return */
return(0);
@@ -166,6 +217,10 @@ int32_t main(void)
static void BootApp_TaskFxn(void* a0, void* a1)
{
+#if defined(BIST_TASK_ENABLED)
+ /* Wait for the BIST task completion */
+ SemaphoreP_pend(gBistTaskCompletedSem, SemaphoreP_WAIT_FOREVER);
+#endif
gtimeBootAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
Boot_App();
@@ -177,6 +232,44 @@ static void BootApp_TaskFxn(void* a0, void* a1)
return;
}
+void BootApp_unlockMmrs(void){
+
+ *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL;
+ *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL;
+
+ *((uint32_t *)(SDL_MCU_CTRL_MMR0_CFG0_BASE + SDL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL;
+ *((uint32_t *)(SDL_MCU_CTRL_MMR0_CFG0_BASE + SDL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL;
+
+ *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL;
+ *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL;
+
+ return;
+}
+
+#if defined(BIST_TASK_ENABLED)
+static void BistApp_TaskFxn(void* a0, void* a1)
+{
+ /* Initialize the SDL osal */
+ SDL_TEST_osalInit();
+
+ gtimeBistAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+ /* Unlock MMRs before BISTs to enable access to LBIST registers */
+ BootApp_unlockMmrs();
+
+ bist_TaskFxn();
+
+ gtimeBistAppFinish = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM));
+
+ UART_printf("\nMCU Bist Task started at %d usecs and finished at %d usecs\r\n", (uint32_t)gtimeBistAppStart, (uint32_t)gtimeBistAppFinish);
+
+ /* Post semaphore after BIST task completion so other tasks could start execution */
+ SemaphoreP_post(gBistTaskCompletedSem);
+
+ return;
+}
+#endif
+
uint32_t Boot_App()
{
uint32_t retVal;
--
2.34.1
Regards,
Josiitaa
Hi Josiitaa,
It seems that I can see the log from MCU UART. But, I did not see any log from Linux UART. Is it right?
I attach the log. Pls refer to it.
[2024-05-30 23:33:55.840]# RECV ASCII>
[2024-05-30 23:33:56.638]# RECV ASCII>
SBL Revision: 01.00.10.01 (Dec 6 2023 - 06:41:51)
[2024-05-30 23:33:56.844]# RECV ASCII>
TIFS ver: 9.1.2--v09.01.02 (Kool Koala)
[2024-05-30 23:33:58.114]# RECV ASCII>
Starting Sciserver..... PASSED
MCU R5F App started at 0 usecs
Starting PBIST failure insertion test on PBIST HWPOST MCU, index 0...
Starting PBIST test on PBIST HWPOST MCU, index 0...
HW POST MCU Status : SDL_PBIST_POST_COMPLETED_SUCCESS
Starting PBIST Test Of ROM on PBIST HWPOST MCU, index 0...
HW POST MCU Status : SDL_LBIST_POST_NOT_RUN
HW POST DMSC Status : SDL_LBIST_POST_NOT_RUN
HW POST MCU Status : SDL_LBIST_POST_NOT_RUN
HW POST DMSC Status : SDL_LBIST_POST_NOT_RUN
Starting PBIST failure insertion test on Main R5F 0 PBIST, index 1...
Starting PBIST failure insertion test on Codec PBIST, index 2...
Starting PBIST failure insertion test on Main Infra1 PBIST, index 3...
Starting PBIST failure insertion test on VPAC PBIST, index 4...
Starting PBIST failure insertion test on DSS EDP PBIST, index 5...
Starting PBIST failure insertion test on DMPAC PBIST, index 6...
Starting PBIST failure insertion test on NAVSS PBIS
[2024-05-30 23:33:58.248]# RECV ASCII>
T, index 7...
Starting PBIST failure insertion test on Main Infra0 PBIST, index 8...
Starting PBIST failure insertion t
[2024-05-30 23:33:59.267]# RECV ASCII>
est on GPU PBIST, index 9...
Starting PBIST failure insertion test on HC PBIST, index 10...
Starting PBIST failure insertion test on VPAC_1 PBIST, index 11...
Starting PBIST failure insertion test on Main R5F 2 PBIST, index 12...
Starting PBIST failure insertion test on Codec 1 PBIST, index 13...
Starting PBIST failure insertion test on A72_0_0 PBIST, index 14...
Starting PBIST failure insertion test on A72_0_1 PBIST, index 15...
Starting PBIST failure insertion test on A72_1_0 PBIST, index 16...
Starting PBIST failure insertion test on A72_1_1 PBIST, index 17...
Starting PBIST failure insertion test on C7X_0 PBIST, index 18...
Starting PBIST failure insertion test on C7X_1 PBIST, index 19...
Starting PBIST failure insertion test on C7X_2 PBIST, index 20...
Starting PBIST failure insertion test on C7X_3 PBIST, index 21...
Starting PBIST failure insertion test on ANA_0 PBIST, index 22...
Starting PBIST failure insertion test on
[2024-05-30 23:33:59.363]# RECV ASCII>
ANA_1 PBIST, index 23...
Starting PBIST failure insertion test on ANA_2 PBIST, index 24...
Startin
[2024-05-30 23:34:00.448]# RECV ASCII>
g PBIST failure insertion test on ANA_3 PBIST, index 25...
Starting PBIST failure insertion test on MSMC PBIST, index 26...
Starting PBIST failure insertion test on Main R5F 1 PBIST, index 27...
Starting PBIST test on Main R5F 0 PBIST, index 1...
Starting PBIST test on Codec PBIST, index 2...
Starting PBIST test on Main Infra1 PBIST, index 3...
Starting PBIST test on VPAC PBIST, index 4...
Starting PBIST test on DSS EDP PBIST, index 5...
Starting PBIST test on DMPAC PBIST, index 6...
Starting PBIST test on NAVSS PBIST, index 7...
Starting PBIST test on Main Infra0 PBIST, index 8...
Starting PBIST test on GPU PBIST, index 9...
Starting PBIST test on HC PBIST, index 10...
Starting PBIST test on VPAC_1 PBIST, index 11...
Starting PBIST test on Main R5F 2 PBIST, index 12...
Starting PBIST test on Codec 1 PBIST, index 13...
Starting PBIST test on A72_0_0 PBIST, index 14...
Starting PBIST test on A72_0_1 PBIST, ind
[2024-05-30 23:34:00.450]# RECV ASCII>
ex 15...
[2024-05-30 23:34:01.520]# RECV ASCII>
Starting PBIST test on A72_1_0 PBIST, index 16...
Starting PBIST test on A72_1_1 PBIST, index 17...
Starting PBIST test on C7X_0 PBIST, index 18...
Starting PBIST test on C7X_1 PBIST, index 19...
Starting PBIST test on C7X_2 PBIST, index 20...
Starting PBIST test on C7X_3 PBIST, index 21...
Starting PBIST test on ANA_0 PBIST, index 22...
Starting PBIST test on ANA_1 PBIST, index 23...
Starting PBIST test on ANA_2 PBIST, index 24...
Starting PBIST test on ANA_3 PBIST, index 25...
Starting PBIST test on MSMC PBIST, index 26...
Starting PBIST test on Main R5F 1 PBIST, index 27...
Starting PBIST Test Of ROM on Main R5F 0 PBIST, index 1...
Starting PBIST Test Of ROM on Codec PBIST, index 2...
Starting PBIST Test Of ROM on Main Infra1 PBIST, index 3...
Starting PBIST Test Of ROM on VPAC PBIST, index 4...
Starting PBIST Test Of ROM on DSS EDP PBIST, index 5...
Starting PBIST Test Of ROM on DMPAC PBIST, index
[2024-05-30 23:34:01.538]# RECV ASCII>
6..
[2024-05-30 23:34:02.530]# RECV ASCII>
.
Starting PBIST Test Of ROM on NAVSS PBIST, index 7...
Starting PBIST Test Of ROM on Main Infra0 PBIST, index 8...
Starting PBIST Test Of ROM on GPU PBIST, index 9...
Starting PBIST Test Of ROM on HC PBIST, index 10...
Starting PBIST Test Of ROM on VPAC_1 PBIST, index 11...
Starting PBIST Test Of ROM on Main R5F 2 PBIST, index 12...
Starting PBIST Test Of ROM on Codec 1 PBIST, index 13...
Starting PBIST Test Of ROM on A72_0_0 PBIST, index 14...
Starting PBIST Test Of ROM on A72_0_1 PBIST, index 15...
Starting PBIST Test Of ROM on A72_1_0 PBIST, index 16...
Starting PBIST Test Of ROM on A72_1_1 PBIST, index 17...
Starting PBIST Test Of ROM on C7X_0 PBIST, index 18...
Starting PBIST Test Of ROM on C7X_1 PBIST, index 19...
Starting PBIST Test Of ROM on C7X_2 PBIST, index 20...
Starting PBIST Test Of ROM on C7X_3 PBIST, index 21...
Starting PBIST Test Of ROM on ANA_0 PBIST, index 22...
Starting PBIST Test Of ROM
[2024-05-30 23:34:02.583]# RECV ASCII>
on ANA_1 PBIST, index 23...
Starting PBIST
[2024-05-30 23:34:03.178]# RECV ASCII>
Test Of ROM on ANA_2 PBIST, index 24...
Starting PBIST Test Of ROM on ANA_3 PBIST, index 25...
Starting PBIST Test Of ROM on MSMC PBIST, index 26...
Starting PBIST Test Of ROM on Main R5F 1 PBIST, index 27...
Starting PBIST Test Of ROM on PBIST MCU PSROM, index 28...
Starting PBIST Test Of ROM on PBIST MCU_1, index 29...
Starting PBIST Test Of ROM on PBIST MCU PULSAR, index 30...
*** Boot stage 0 is complete, cores for this stage may now be loaded ***
[2024-05-30 23:34:03.457]# RECV ASCII>
*** Boot stage 1 is complete, cores for this stage may now be loaded ***
[2024-05-30 23:34:04.563]# RECV ASCII>
*** Boot stage 2 is complete, cores for this stage may now be loaded ***
==========================
BIST: Example App Summary:
==========================
BIST: Pre-boot Stage - Ran negative PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
Pre-boot stage - Ran 1 negative PBIST total sections
BIST: Pre-boot Stage - Ran ROM Test PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
Pre-boot stage - Ran 1 ROM Test of PBIST total sections
BIST: Pre-boot Stage - Ran PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
Pre-boot stage - Ran 1 PBIST total sections
BIST: Pre-boot Stage - Ran LBIST ID - LBIST_HWPOST_INST_SMS_INDEX, Result = LBIST_POST_COMPLETED_SUCCESS
BIST: Pre-boot Stage - Ran LBIST ID - LBIST_HWPOST_INST_MCU_INDEX, Result = LBIST_POST_COMPLETED_SUCCESS
Pre-boot stage - Ran 2 LBIST total sections
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAINR5F0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_CODEC, Result = PASS
BIST: Stage 0 - Ran nega
[2024-05-30 23:34:04.612]# RECV ASCII>
tive PBIST ID - PBIST_INSTANCE_MAININFRA_1, Result = PASS
[2024-05-30 23:34:05.632]# RECV ASCII>
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_VPAC_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_DSS, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_NAVSS, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAININFRA_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_GPU, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_HC, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_VPAC_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAINR5F2, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_CODEC_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_0_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_0_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_1_0, Result = PASS
[2024-05-30 23:34:05.708]# RECV ASCII>
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_1_1
[2024-05-30 23:34:06.721]# RECV ASCII>
, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_2, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_3, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_2, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_3, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MSMC, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAINR5F1, Result = PASS
BIST: Stage 0 - Ran 30 negative PBIST total sections
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAINR5F0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_CODEC, Result = PASS
BIST: Stag
[2024-05-30 23:34:06.790]# RECV ASCII>
e 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAININFRA_1, Result
[2024-05-30 23:34:07.808]# RECV ASCII>
= PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_VPAC_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_DSS, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_NAVSS, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAININFRA_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_GPU, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_HC, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_VPAC_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAINR5F2, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_CODEC_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_0_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_0_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_1_0, Resu
[2024-05-30 23:34:07.883]# RECV ASCII>
lt = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTAN
[2024-05-30 23:34:08.899]# RECV ASCII>
CE_A72_1_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_2, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_3, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_2, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_3, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MSMC, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAINR5F1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MCU_PSROM, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MCU_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE
[2024-05-30 23:34:09.009]# RECV ASCII>
_MCU_PULSAR, Result = PASS
BIST: Stage 0 - Ran 30 ROM Test PBIST total sections
BIST: Stage 0 - Ran PBIST ID
[2024-05-30 23:34:10.034]# RECV ASCII>
- PBIST_INSTANCE_MAINR5F0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_CODEC, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAININFRA_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_VPAC_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_DSS, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_NAVSS, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAININFRA_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_GPU, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_HC, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_VPAC_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAINR5F2, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_CODEC_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_0_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_0_1, Result = PASS
[2024-05-30 23:34:10.104]# RECV ASCII>
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_1_0, Result
[2024-05-30 23:34:11.136]# RECV ASCII>
= PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_1_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_2, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_3, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_2, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_3, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MSMC, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAINR5F1, Result = PASS
BIST: Stage 0 - Ran 30 PBIST total sections
BIST: Stage 0 - Ran LBIST ID - LBIST_INST_MAINR5F0_INDEX, Result = PASS
BIST: Stage 0 - Ran LBIST ID - LBIST_INST_MAINR5F2_INDEX, Result = PASS
BIST: Stage 0 - Ran 2 LBIST sections
BIST: Stage 1 - Ran
[2024-05-30 23:34:11.214]# RECV ASCII>
0 negative PBIST total sections
BIST: Stage 1 - Ran 0 ROM Test PBIST total s
[2024-05-30 23:34:12.227]# RECV ASCII>
ections
BIST: Stage 1 - Ran 0 PBIST total sections
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_MAINR5F1_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X0_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X1_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X2_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X3_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_VPAC0_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_DMPAC_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_A72_0_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_A72_1_INDEX, Result = PASS
BIST: Stage 1 - Ran 9 LBIST sections
BIST: Stage 2 - Ran 0 negative PBIST total sections
BIST: Stage 2 - Ran 0 ROM Test PBIST total sections
BIST: Stage 2 - Ran 0 PBIST total sections
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE0_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE1_INDEX,
[2024-05-30 23:34:12.293]# RECV ASCII>
Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS
[2024-05-30 23:34:12.869]# RECV ASCII>
0_CORE2_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE3_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE0_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE1_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE2_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE3_INDEX, Result = PASS
BIST: Stage 2 - Ran 8 LBIST sections
MCU Bist Task started at 27 usecs and finished at 622368 usecs
I followed the same steps as the J721E:
Generate lateapps by using the following commands
goto <RTOS SDK>/<PDK>/packages/ti/boot/sbl/example/boot_app/scripts
Run ./generate_lateapps.sh j721e_evm
Multicore images(lateapps) will be generated in <PDK>/packages/ti/boot/sbl/example/boot_app/multicore_images/j721e_evm/.
multicore_MCU2_0_MCU2_1_stage1.appimage corresponds to lateapp1, multicore_DSPs_MCU3_0_MCU3_1_MCU4_0_MCU4_1_stage2.appimage corresponds to lateapp2 and multicore_MPU1_0_stage3.appimage corresponds to lateapp3.
Copy sbl_mmcsd_img_mcu1_0_release.tiimage present in <PDK>/packages/ti/boot/sbl/binary/j721e_evm/mmcsd/bin as tiboot3.bin to the boot partition of SD card
Copy tifs.bin present in <PDK>/packages/ti/drv/sciclient/soc/V6 to the boot partition of SD card.
goto <RTOS SDK>/<PDK>/packages/ti/build and build boot_app_mmcsd_linux by using the following command:
make BOARD=j784s4_evm CORE=mcu1_0 boot_app_mmcsd_linux -sj
Copy sbl_boot_app_mmcsd_linux_j721e_evm_mcu1_0_freertos_TestApp_release.appimage present in <PDK>/packages/ti/boot/sbl/example/boot_app/binary/j721e_evm/mmcsd as app to the boot partition of SD card.
Copy stage1 image as lateapp1, stage2 image as lateapp2 and stage3 image as lateapp3 to the boot partition of SD card.
Copy atf_optee.appimage, tidtb_linux.appimage, tikernelimage_linux.appimage present in<PDK>/packages/ti/boot/sbl/tools/BootApp_binaries/linux/j721e_evm to the boot partition of SD card.
Hi,
Were you getting Linux logs before BIST integration?
Regards,
Josiitaa
Yes. You can refer to the attachment. I built the boot app without your patch and got the linux log.
[2024-06-03 22:41:53.287]# RECV ASCII>
[2024-06-03 22:42:06.521]# RECV ASCII>
NOTICE: BL31: v2.9(release):v2.9.0-614-gd7a7135d32-dirty
NOTICE: BL31: Built : 09:34:15, Aug 24 2023
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC:
I/TC: OP-TEE version: 3.20.0 (gcc version 11.4.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[ 0.000000] Linux version 6.1.46-g37f154cc9c (oe-user@oe-host) (aarch64-oe-linux-gcc (GCC) 11.4.0, GNU ld (GNU Binutils) 2.38.20220708) #
[2024-06-03 22:42:06.601]# RECV ASCII>
1 SMP PREEMPT Thu Oct 26 19:24:34 UTC 2023
[ 0.000000] Machine model: Texas Instruments J784S4 EVM
[ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002880000 (options '')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
[ 0.000000] efi: UEFI not found.
[ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000f90000000, size 1792 MiB
[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000,
[2024-06-03 22:42:06.697]# RECV ASCII>
size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
[ 0.000000] OF: reserved mem:
[2024-06-03 22:42:06.792]# RECV ASCII>
initialized node r5f-memory@a3100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a6000000, compat
[2024-06-03 22:42:06.873]# RECV ASCII>
ible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a6100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a7000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node r5f-memory@a7100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool
[ 0.000000] Reserved
[2024-06-03 22:42:06.969]# RECV ASCII>
memory: created DMA memory pool at 0x00000000a9000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node c71-dma-memory@a9000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a9100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node c71-memory@a9100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node c71-dma-memory@aa000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000aa100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node c71-memory@aa100000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000000ab000000, size 1 MiB
[ 0.000000] OF: reserved mem: initialized node c71-dma-memory@ab000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000
[2024-06-03 22:42:07.032]# RECV ASCII>
0ab100000, size 15 MiB
[ 0.000000] OF: reserved mem: initialized node c71-memory@ab100000, compatible id shared-dma-pool
[2024-06-03 22:42:07.790]# RECV ASCII>
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x0000000fffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x000000009e7fffff]
[ 0.000000] node 0: [mem 0x000000009e800000-0x00000000abffffff]
[ 0.000000] node 0: [mem 0x00000000ac000000-0x00000000ffffffff]
[ 0.000000] node 0: [mem 0x0000000880000000-0x0000000fffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x0000000fffffffff]
[2024-06-03 22:42:07.945]# RECV ASCII>
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: Trusted OS migration not required
[ 0.000000] psci: SMC Calling Convention v1.4
[ 0.000000] percpu: Embedded 19 pages/cpu s38376 r8192 d31256 u77824
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] CPU features: detected: Spectre-v3a
[ 0.000000] CPU features: detected: Spectre-BHB
[ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
[ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[ 0.000000] CPU features: detected: ARM erratum 1742098
[ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[ 0.000000] alternatives: applying boot alternatives
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 8257536
[ 0.000000] Kernel
[2024-06-03 22:42:08.055]# RECV ASCII>
command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02880000 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait
[ 0.000000] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] software IO TLB: area num 8.
[ 0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[2024-06-03 22:42:08.504]# RECV ASCII>
[ 0.000000] Memory: 30770392K/33554432K available (13056K kernel code, 1300K rwdata, 4440K rodata, 2176K init, 503K bss, 949032K reserved, 1835008K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
[ 0.000000] Trampoline variant of Tasks RCU enabled.
[ 0.000000] Tracing variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GICv3: [Firmware Bug]: GICR region 0x0000000001900000 has overlapping address
[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[ 0.000000] GICv3: 960 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[2024-06-03 22:42:08.601]# RECV ASCII>
[ 0.000000] Root IRQ handler: gic_handle_irq
[ 0.000000] GICv3: GICv3 features: 16 PPIs
[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[ 0.000000] ITS [mem 0x01820000-0x0182ffff]
[ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[ 0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[ 0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
[ 0.000000] ITS: using cache flushing for cmd queue
[ 0.000000] GICv3: using LPI property table @0x0000000880050000
[ 0.000000] GIC: using cache flushing for LPI property table
[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880060000
[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 44
[2024-06-03 22:42:08.697]# RECV ASCII>
0795210634 ns
[ 0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[ 0.010542] Console: colour dummy device 80x25
[ 0.016258] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[ 0.029600] pid_max: default: 32768 minimum: 301
[ 0.035531] LSM: Security Framework initializing
[ 0.041559] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.051318] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.062856] cblist_init_generic: Setting adjustable number of callback queues.
[ 0.072123] cblist_init_generic: Setting shift to 3 and lim to 1.
[ 0.079959] cblist_init_generic: Setting adjustable number of callback queues.
[ 0.089193] cblist_init_generic: Setting shift to 3 and lim to 1.
[ 0.097083] rcu: Hierarchical SRCU implementation.
[ 0.103206] rcu: Max phase no-delay instances is 1000.
[ 0.110109] Platform MSI: msi-control
[2024-06-03 22:42:08.793]# RECV ASCII>
ler@1820000 domain created
[ 0.117927] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[ 0.130136] EFI services will not be available.
[ 0.136241] smp: Bringing up secondary CPUs ...
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 2 initializing
I/TC: Secondary CPU 2 switching to normal world boot
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 3 initializing
I/TC: Secondary CPU 3 switching to normal world boot
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 2 initializing
I/TC: Secondary CPU 2 switching to normal world boot
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 3 initializing
I/TC: Secondary CPU 3 switching to normal world boot
ERROR:
[2024-06-03 22:42:08.889]# RECV ASCII>
GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 4 initializing
I/TC: Secondary CPU 4 switching to normal world boot
ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 5 initializing
I/TC: Secondary CPU 5 switching to normal world boot
[ 0.159909] Detected PIPT I-cache on CPU1
[ 0.159993] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[ 0.160012] GICv3: CPU1: using allocated LPI pending table @0x0000000880070000
[ 0.160055] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[ 0.177993] Detected PIPT I-cache on CPU2
[ 0.178071] GICv3: CPU2: found redistributor 2 region 0:0x0000000001940000
[ 0.178088] GICv3: CPU2: using allocated LPI pending table @0x0000000880080000
[ 0.178119] CPU2: Booted secondary processor 0x0000000002 [0x411fd080]
[ 0.195994] Detected PIPT I-cache on CPU3
[ 0.196056] GICv3: CPU3: found redistributor 3 region 0:0x0000000001960000
[ 0.196073] GICv3: CPU3: u
[2024-06-03 22:42:08.969]# RECV ASCII>
sing allocated LPI pending table @0x0000000880090000
[ 0.196101] CPU3: Booted secondary processor 0x0000000003 [0x411fd080]
[ 0.214014] Detected PIPT I-cache on CPU4
[ 0.214121] GICv3: CPU4: found redistributor 100 region 0:0x0000000001980000
[ 0.214138] GICv3: CPU4: using allocated LPI pending table @0x00000008800a0000
[ 0.214178] CPU4: Booted secondary processor 0x0000000100 [0x411fd080]
[ 0.232121] Detected PIPT I-cache on CPU5
[ 0.232199] GICv3: CPU5: found redistributor 101 region 0:0x00000000019a0000
[ 0.232215] GICv3: CPU5: using allocated LPI pending table @0x00000008800b0000
[ 0.232247] CPU5: Booted secondary processor 0x0000000101 [0x411fd080]
[ 0.250138] Detected PIPT I-cache on CPU6
[ 0.250219] GICv3: CPU6: found redistributor 102 region 0:0x00000000019c0000
[ 0.250235] GICv3: CPU6: using allocated LPI pending table @0x00000008800c0000
[ 0.250268] CPU6: Booted secondary processor 0x0000000102 [0x411fd080]
[ 0.268156] Detected PIPT I-cache on
[2024-06-03 22:42:09.097]# RECV ASCII>
CPU7
[ 0.268233] GICv3: CPU7: found redistributor 103 region 0:0x00000000019e0000
[ 0.268249] GICv3: CPU7: using allocated LPI pending table @0x00000008800d0000
[ 0.268281] CPU7: Booted secondary processor 0x0000000103 [0x411fd080]
[ 0.268345] smp: Brought up 1 node, 8 CPUs
[ 0.494588] SMP: Total of 8 processors activated.
[ 0.500595] CPU features: detected: 32-bit EL0 Support
[ 0.507164] CPU features: detected: CRC32 instructions
[ 0.513795] CPU: All CPU(s) started at EL2
[ 0.519025] alternatives: applying system-wide alternatives
[ 0.527522] devtmpfs: initialized
[ 0.544400] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.556885] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
[ 0.596018] pinctrl core: initialized pinctrl subsystem
[ 0.603179] DMI not present or invalid.
[ 0.608564] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.617837] DMA: preallocated 4096 KiB GFP_K
[2024-06-03 22:42:09.209]# RECV ASCII>
ERNEL pool for atomic allocations
[ 0.627876] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[ 0.638789] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[ 0.649106] audit: initializing netlink subsys (disabled)
[ 0.656182] audit: type=2000 audit(0.428:1): state=initialized audit_enabled=0 res=1
[ 0.656487] thermal_sys: Registered thermal governor 'step_wise'
[ 0.666105] thermal_sys: Registered thermal governor 'power_allocator'
[ 0.673914] cpuidle: using governor menu
[ 0.687363] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.696181] ASID allocator initialised with 32768 entries
[ 0.715000] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
[ 0.725375] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/i2c@2040000/dsi-edp-bridge@2c
[ 0.737887] platform a000000.dp-bridge: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
[ 0.751447] platform
[2024-06-03 22:42:09.305]# RECV ASCII>
a000000.dp-bridge: Fixed dependency cycle(s) with /dp0-connector
[ 0.762510] KASLR enabled
[ 0.769911] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[ 0.778591] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[ 0.786597] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[ 0.795266] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[ 0.803270] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.811938] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[ 0.819941] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[ 0.828609] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[ 0.838005] k3-chipinfo 43000014.chipid: Family:J784S4 rev:SR1.0 JTAGID[0x0bb8002f] Detected
[ 0.850001] iommu: Default domain type: Translated
[ 0.856243] iommu: DMA domain TLB invalidation policy: strict mode
[ 0.864441] SCSI subsystem initialized
[ 0.869466] usbcore: registered new interface driver usbf
[2024-06-03 22:42:09.308]# RECV ASCII>
s
[ 0.876496] usbcore: registered new interface driver hub
[ 0.883296] usbcore: registered new d
[2024-06-03 22:42:09.416]# RECV ASCII>
evice driver usb
[ 0.890156] pps_core: LinuxPPS API ver. 1 registered
[ 0.896500] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.908176] PTP clock support registered
[ 0.913286] EDAC MC: Ver: 3.0.0
[ 0.918079] FPGA manager framework
[ 0.922470] Advanced Linux Sound Architecture Driver Initialized.
[ 0.930849] clocksource: Switched to clocksource arch_sys_counter
[ 0.938818] VFS: Disk quotas dquot_6.6.0
[ 0.943862] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.956483] NET: Registered PF_INET protocol family
[ 0.963217] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.979331] tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, linear)
[ 0.990637] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 1.000577] TCP established hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 1.011944] TCP bind hash table
[2024-06-03 22:42:09.512]# RECV ASCII>
entries: 65536 (order: 9, 2097152 bytes, linear)
[ 1.022586] TCP: Hash tables configured (established 262144 bind 65536)
[ 1.031227] UDP hash table entries: 16384 (order: 7, 524288 bytes, linear)
[ 1.040432] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, linear)
[ 1.050344] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 1.058017] RPC: Registered named UNIX socket transport module.
[ 1.065599] RPC: Registered udp transport module.
[ 1.071604] RPC: Registered tcp transport module.
[ 1.077607] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.085839] NET: Registered PF_XDP protocol family
[ 1.091967] PCI: CLS 0 bytes, default 64
[ 1.097860] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[ 1.109579] Initialise system trusted keyrings
[ 1.115454] workingset: timestamp_bits=46 max_order=23 bucket_order=0
[ 1.126989] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 1.134881] NFS: Registering th
[2024-06-03 22:42:09.624]# RECV ASCII>
e id_resolver key type
[ 1.141359] Key type id_resolver registered
[ 1.146698] Key type id_legacy registered
[ 1.151854] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 1.160416] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[ 1.169991] 9p: Installing v9fs 9p2000 file system support
[ 1.201310] Key type asymmetric registered
[ 1.206543] Asymmetric key parser 'x509' registered
[ 1.212823] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[ 1.222378] io scheduler mq-deadline registered
[ 1.228171] io scheduler kyber registered
[ 1.236467] pinctrl-single 4301c000.pinctrl: 13 pins, size 52
[ 1.243934] pinctrl-single 4301c038.pinctrl: 11 pins, size 44
[ 1.251518] pinctrl-single 4301c068.pinctrl: 72 pins, size 288
[ 1.259082] pinctrl-single 4301c190.pinctrl: 1 pins, size 4
[ 1.266379] pinctrl-single 11c000.pinctrl: 72 pins, size 288
[ 1.274192] pinctrl-single a40000.pinctrl: 512 pins, size 2048
[2024-06-03 22:42:09.737]# RECV ASCII>
[ 1.287899] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 1.302634] loop: module loaded
[ 1.307755] megasas: 07.719.03.00-rc1
[ 1.315474] tun: Universal TUN/TAP device driver, 1.6
[ 1.322421] thunder_xcv, ver 1.0
[ 1.326573] thunder_bgx, ver 1.0
[ 1.330707] nicpf, ver 1.0
[ 1.334529] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
[ 1.343758] hns3: Copyright (c) 2017 Huawei Corporation.
[ 1.350570] hclge is initializing
[ 1.354813] e1000: Intel(R) PRO/1000 Network Driver
[ 1.361040] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 1.368397] e1000e: Intel(R) PRO/1000 Network Driver
[ 1.374735] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 1.382319] igb: Intel(R) Gigabit Ethernet Network Driver
[ 1.389214] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 1.396345] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[ 1.404349] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 1.412022] s
[2024-06-03 22:42:09.832]# RECV ASCII>
ky2: driver version 1.30
[ 1.417292] VFIO - User Level meta-driver version: 0.3
[ 1.424431] usbcore: registered new interface driver usb-storage
[ 1.432750] i2c_dev: i2c /dev entries driver
[ 1.439488] sdhci: Secure Digital Host Controller Interface driver
[ 1.447390] sdhci: Copyright(c) Pierre Ossman
[ 1.453364] Synopsys Designware Multimedia Card Interface Driver
[ 1.461418] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.469489] ledtrig-cpu: registered to indicate activity on CPUs
[ 1.477347] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[ 1.485810] usbcore: registered new interface driver usbhid
[ 1.492931] usbhid: USB HID core driver
[ 1.498898] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[ 1.504596] optee: revision 3.20 (8e74d476)
[ 1.525122] optee: dynamic sha
[2024-06-03 22:42:10.008]# RECV ASCII>
red memory is enabled
[ 1.536981] optee: initialized driver
[ 1.543381] Initializing XFRM netlink socket
[ 1.548876] NET: Registered PF_PACKET protocol family
[ 1.555428] 9pnet: Installing 9P2000 support
[ 1.560931] Key type dns_resolver registered
[ 1.566659] registered taskstats version 1
[ 1.571915] Loading compiled-in X.509 certificates
[ 1.586834] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
[ 1.641739] omap_i2c 42120000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.649946] pca953x 0-0020: supply vcc not found, using dummy regulator
[ 1.658537] pca953x 0-0020: using no AI
[ 1.687713] pca953x 0-0022: supply vcc not found, using dummy regulator
[ 1.696228] pca953x 0-0022: using AI
[ 1.701619] omap_i2c 2000000.i2c: bus 0 rev0.12 at 400 kHz
[ 1.709334] pca953x 2-0020: supply vcc not found, using dummy regulator
[ 1.717855] pca953x 2-0020: using no AI
[ 1.743505] omap_i2c 2040000.i2c: bus 2 rev0.12 at
[2024-06-03 22:42:10.120]# RECV ASCII>
400 kHz
[ 1.751445] pca953x 3-0020: supply vcc not found, using dummy regulator
[ 1.760010] pca953x 3-0020: using no AI
[ 1.787262] omap_i2c 2050000.i2c: bus 3 rev0.12 at 400 kHz
[ 1.794550] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 177 domain created
[ 1.805230] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 10 domain created
[ 1.816793] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 283 domain created
[ 1.827633] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 321 created
[ 1.844547] ti-udma 311a0000.dma-controller: Number of rings: 48
[ 1.853047] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
[ 1.864633] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:328
[ 1.876994] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[ 1.885444] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[ 1.89661
[2024-06-03 22:42:10.250]# RECV ASCII>
6] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:315
[ 1.909316] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[ 1.917766] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[ 1.927806] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 216, base_baud = 6000000) is a 8250
[ 1.939741] 2880000.serial: ttyS2 at MMIO 0x2880000 (irq = 217, base_baud = 3000000) is a 8250
[ 1.950820] printk: console [ttyS2] enabled
[ 1.950820] printk: console [ttyS2] enabled
[ 1.961378] printk: bootconsole [ns16550a0] disabled
[ 1.961378] printk: bootconsole [ns16550a0] disabled
[ 2.014870] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 2.025843] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
[ 2.036185] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 2.052304] am65-cp
[2024-06-03 22:42:10.299]# RECV ASCII>
sw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 2.061317] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 2.069052] pps pps0: new PPS source ptp0
[ 2.074275] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[ 2.126847] davinci_mdio c2
[2024-06-03 22:42:10.456]# RECV ASCII>
00f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 2.137588] davinci_mdio c200f00.mdio: phy[0]: device c200f00.mdio:00, driver TI DP83867
[ 2.147715] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 2.163684] am65-cpsw-nuss c200000.ethernet: Use random MAC address
[ 2.171529] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4
[ 2.180435] am65-cpsw-nuss c200000.ethernet: ALE Table size 64
[ 2.188192] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[ 2.201031] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[ 2.212223] mmc0: CQHCI version 5.10
[ 2.257901] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[2024-06-03 22:42:10.566]# RECV ASCII>
[ 2.357380] mmc0: Command Queue Engine enabled
[ 2.362945] mmc0: new HS200 MMC card at address 0001
[ 2.369676] mmcblk0: mmc0:0001 G1M15L 29.6 GiB
[ 2.376966] mmcblk0boot0: mmc0:0001 G1M15L 31.5 MiB
[ 2.384173] mmcblk0boot1: mmc0:0001 G1M15L 31.5 MiB
[ 2.391266] mmcblk0rpmb: mmc0:0001 G1M15L 4.00 MiB, chardev (240:0)
[2024-06-03 22:42:10.747]# RECV ASCII>
[ 2.549407] tps6594-rtc tps6594-rtc.4.auto: registered as rtc0
[ 2.556864] tps6594-rtc tps6594-rtc.4.auto: hctosys: unable to read the hardware clock
[ 2.567262] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
[ 2.575777] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
[ 2.584273] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
[ 2.592760] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fca100
[ 2.601249] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
[ 2.609741] omap-mailbox 31f85000.mailbox: omap mailbox rev 0x66fca100
[ 2.621550] ti-udma 285c0000.dma-controller: Channels: 22 (tchan: 11, rchan: 11, gp-rflow: 8)
[ 2.634178] ti-udma 31150000.dma-controller: Channels: 66 (tchan: 33, rchan: 33, gp-rflow: 16)
[ 2.648881] spi-nor spi0.0: unrecognized JEDEC id bytes: ff ef dc 21 00 00
[ 2.659837] spi-nor spi1.0: mt25qu512a (65536 Kbytes)
[ 2.666214] 7 fixed-partitions partitions found on MTD device 47050000.spi.0
[
[2024-06-03 22:42:10.874]# RECV ASCII>
2.675010] Creating 7 MTD partitions on "47050000.spi.0":
[ 2.681849] 0x000000000000-0x000000080000 : "qspi.tiboot3"
[ 2.689680] 0x000000080000-0x000000280000 : "qspi.tispl"
[ 2.697080] 0x000000280000-0x000000680000 : "qspi.u-boot"
[ 2.704564] 0x000000680000-0x0000006c0000 : "qspi.env"
[ 2.711746] 0x0000006c0000-0x000000700000 : "qspi.env.backup"
[ 2.719707] 0x000000800000-0x000003fc0000 : "qspi.rootfs"
[ 2.727193] 0x000003fc0000-0x000004000000 : "qspi.phypattern"
[ 2.774874] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 2.785885] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
[ 2.796232] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 2.812365] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[ 2.821378] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[ 2.829174] pps pps0: new PPS source pt
[2024-06-03 22:42:11.003]# RECV ASCII>
p1
[ 2.834372] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[ 2.846756] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[ 2.894875] davinci_mdio c200f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[ 2.905666] davinci_mdio c200f00.mdio: phy[0]: device c200f00.mdio:00, driver TI DP83867
[ 2.915802] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[ 2.931776] am65-cpsw-nuss c200000.ethernet: Use random MAC address
[ 2.939599] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4
[ 2.948496] am65-cpsw-nuss c200000.ethernet: ALE Table size 64
[ 2.956295] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[ 2.968639] am65-cpsw-nuss c200000.ethernet: set new flow-id-base 82
[ 2.978874] debugfs: Directory 'pd:74' with parent 'pm_genpd' already present!
[ 2.979039] mmc1: CQHCI version 5.1
[2024-06-03 22:42:11.159]# RECV ASCII>
0
[ 2.987925] debugfs: Directory 'pd:73' with parent 'pm_genpd' already present!
[ 3.001419] debugfs: Directory 'pd:72' with parent 'pm_genpd' already present!
[ 3.011122] debugfs: Directory 'pd:335' with parent 'pm_genpd' already present!
[ 3.020263] debugfs: Directory 'pd:333' with parent 'pm_genpd' already present!
[ 3.029463] debugfs: Directory 'pd:332' with parent 'pm_genpd' already present!
[ 3.033536] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[ 3.057666] ALSA device list:
[ 3.061390] No soundcards found.
[ 3.065944] Waiting for root device /dev/mmcblk1p2...
[ 3.105359] mmc1: new ultra high speed SDR104 SDHC card at address aaaa
[ 3.114253] mmcblk1: mmc1:aaaa SL32G 29.7 GiB
[ 3.125474] mmcblk1: p1 p2
[ 3.156502] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Quota mode: none.
[ 3.167224] VFS: Mounted root (ext4 filesystem) on device 179:98.
[ 3.182615] devtmpfs: mounted
[ 3.187450] Freeing un
[2024-06-03 22:42:11.204]# RECV ASCII>
used kernel memory: 2176K
[ 3.193252] Run /sbin/init as init process
[2024-06-03 22:42:11.392]# RECV ASCII>
[ 3.357981] systemd[1]: System time before build time, advancing clock.
[ 3.404443] systemd[1]: systemd 244.5+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[ 3.431797] systemd[1]: Detected architecture arm64.
[2024-06-03 22:42:11.485]# RECV ASCII>
Welcome to [1mArago 2021.09[0m!
[ 3.518249] systemd[1]: Set hostname to <j784s4-evm>.
[2024-06-03 22:42:11.674]# RECV ASCII>
[ 3.713909] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[ 3.725051] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6.
[ 3.754115] systemd[1]: /lib/systemd/system/docker.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/docker.sock 鈫?/run/docker.sock; please update the unit file accordingly.
[2024-06-03 22:42:12.375]# RECV ASCII>
[ 4.542848] random: crng init done
[ 4.549597] systemd[1]: Created slice system-getty.slice.
[[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
[ 4.576046] systemd[1]: Created slice system-serial\x2dgetty.slice.
[[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
[ 4.603845] systemd[1]: Created slice User and Session Slice.
[[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
[ 4.627090] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[[0;32m OK [0m] Started [0;1;39mDispatch Password 鈥s to Console Directory Watch[0m.
[ 4.655011] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[[0;32m OK [0m] Started [0;1;39mForward Password R鈥ests to Wall Directory Watch[0m.
[ 4.683044] systemd[1]: Reached target Paths.
[[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
[ 4.698927] systemd[1]: Reached target Remote File Systems.
[[0;32m OK [0m] Reached tar
[2024-06-03 22:42:12.551]# RECV ASCII>
get [0;1;39mRemote File Systems[0m.
[ 4.722909] systemd[1]: Reached target Slices.
[[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
[ 4.738918] systemd[1]: Reached target Swap.
[[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
[ 4.786494] systemd[1]: Listening on RPCbind Server Activation Socket.
[[0;32m OK [0m] Listening on [0;1;39mRPCbind Server Activation Socket[0m.
[ 4.815062] systemd[1]: Reached target RPC Port Mapper.
[[0;32m OK [0m] Reached target [0;1;39mRPC Port Mapper[0m.
[ 4.845012] systemd[1]: Listening on Process Core Dump Socket.
[[0;32m OK [0m] Listening on [0;1;39mProcess Core Dump Socket[0m.
[ 4.871132] systemd[1]: Listening on initctl Compatibility Named Pipe.
[[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
[ 4.901099] systemd[1]: Listening on Journal Audit Socket.
[[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
[ 4.927176] systemd[1]: Listening on Journal Socket (/dev/lo
[2024-06-03 22:42:12.726]# RECV ASCII>
g).
[[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
[ 4.951266] systemd[1]: Listening on Journal Socket.
[[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
[ 4.967279] systemd[1]: Listening on Network Service Netlink Socket.
[[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
[ 4.991199] systemd[1]: Listening on udev Control Socket.
[[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
[ 5.015063] systemd[1]: Listening on udev Kernel Socket.
[[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
[ 5.059292] systemd[1]: Mounting Huge Pages File System...
Mounting [0;1;39mHuge Pages File System[0m...
[ 5.078368] systemd[1]: Mounting POSIX Message Queue File System...
Mounting [0;1;39mPOSIX Message Queue File System[0m...
[ 5.123349] systemd[1]: Mounting Kernel Debug File System...
Mounting [0;1;39mKernel Debug File System[0m...
[ 5.149631] systemd[1]: Mou
[2024-06-03 22:42:12.886]# RECV ASCII>
nting Temporary Directory (/tmp)...
Mounting [0;1;39mTemporary Directory (/tmp)[0m...
[ 5.167178] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped.
[ 5.199531] systemd[1]: Starting Start psplash boot splash screen...
Starting [0;1;39mStart psplash boot splash screen[0m...
[ 5.231418] systemd[1]: Starting RPC Bind...
Starting [0;1;39mRPC Bind[0m...
[ 5.247150] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[ 5.263263] systemd[1]: Starting Journal Service...
Starting [0;1;39mJournal Service[0m...
[ 5.291904] systemd[1]: Starting Load Kernel Modules...
Starting [0;1;39mLoad Kernel Modules[0m...
[ 5.314799] systemd[1]: Starting Remount Root and Kernel File Systems...
Starting [0;1;39mRemount Root and Kernel File Systems[0m...
[ 5.332278] EXT4-fs (mmcblk1p2): re-mounted. Quota mode: none.
[ 5.346632] syste
[2024-06-03 22:42:13.078]# RECV ASCII>
md[1]: Starting udev Coldplug all Devices...
Starting [0;1;39mudev Coldplug all Devices[0m...
[ 5.367551] systemd[1]: Started RPC Bind.
[[0;32m OK [0m] Started [0;1;39mRPC Bind[0m.
[ 5.387556] systemd[1]: Started Journal Service.
[[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
[[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
[[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
[[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
[[0;32m OK [0m] Mounted [0;1;39mTemporary Directory (/tmp)[0m.
[[0;1;31mFAILED[0m] Failed to start [0;1;39mStart psplash boot splash screen[0m.
See 'systemctl status psplash-start.service' for details.
[[0;1;38;5;185mDEPEND[0m] Dependency failed for [0;1;39mStar鈥rogress communication helper[0m.
[[0;1;31mFAILED[0m] Failed to start [0;1;39mLoad Kernel Modules[0m.
See 'systemctl status systemd-modules-load.service' for details.
[[0;32m OK [0m] Started [0;1;39mRemou
[2024-06-03 22:42:13.275]# RECV ASCII>
nt Root and Kernel File Systems[0m.
Mounting [0;1;39mKernel Configuration File System[0m...
Starting [0;1;39mFlush Journal to Persistent Storage[0m...
[ 5.662487] systemd-journald[211]: Received client request to flush runtime journal.
Starting [0;1;39mApply Kernel Variables[0m...
Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
[[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
[[0;32m OK [0m] Started [0;1;39mFlush Journal to Persistent Storage[0m.
[[0;32m OK [0m] Started [0;1;39mApply Kernel Variables[0m.
[[0;32m OK [0m] Started [0;1;39mCreate Static Device Nodes in /dev[0m.
[[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
[2024-06-03 22:42:13.401]# RECV ASCII>
Mounting [0;1;39m/media/ram[0m...
Mounting [0;1;39m/var/volatile[0m...
[ 5.889260] audit: type=1334 audit(1667152340.528:2): prog-id=5 op=LOAD
[ 5.897612] audit: type=1334 audit(1667152340.536:3): prog-id=6 op=LOAD
Starting [0;1;39mudev Kernel Device Manager[0m...
[[0;32m OK [0m] Mounted [0;1;39m/media/ram[0m.
[[0;32m OK [0m] Started [0;1;39mudev Coldplug all Devices[0m.
[[0;32m OK [0m] Mounted [0;1;39m/var/volatile[0m.
[2024-06-03 22:42:13.666]# RECV ASCII>
Starting [0;1;39mudev Wait for Complete Device Initialization[0m...
Starting [0;1;39mLoad/Save Random Seed[0m...
[[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
Starting [0;1;39mCreate Volatile Files and Directories[0m...
[[0;32m OK [0m] Started [0;1;39mudev Kernel Device Manager[0m.
[[0;32m OK [0m] Started [0;1;39mLoad/Save Random Seed[0m.
[[0;32m OK [0m] Started [0;1;39mCreate Volatile Files and Directories[0m.
Starting [0;1;39mNetwork Time Synchronization[0m...
Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
[[0;32m OK [0m] Started [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
[2024-06-03 22:42:13.790]# RECV ASCII>
[[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
[[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
[[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
[2024-06-03 22:42:14.468]# RECV ASCII>
[[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dfsck.slice[0m.
[2024-06-03 22:42:14.694]# RECV ASCII>
[[0;32m OK [0m] Found device [0;1;39m/dev/mmcblk1p1[0m.
[[0;32m OK [0m] Started [0;1;39mudev Wait for Complete Device Initialization[0m.
[[0;32m OK [0m] Started [0;1;39mHardware RNG Entropy Gatherer Daemon[0m.
[[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
[[0;32m OK [0m] Started [0;1;39mDaily rotation of log files[0m.
[[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
[[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
[[0;32m OK [0m] Listening on [0;1;39mAvahi mDNS/DNS-SD Stack Activation Socket[0m.
[[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
Starting [0;1;39mDocker Socket for the API[0m.
[[0;32m OK [0m] Listening on [0;1;39mdropbear.socket[0m.
Starting [0;1;39mReboot and dump vmcore via kexec[0m...
Starting [0;1;39mFile System Check on /dev/mmcblk1p1[0m...
[[0;32m OK [0m] Listening on [0;1;39mDocker Socket for the API[0m.
[[0;
[2024-06-03 22:42:14.841]# RECV ASCII>
32m OK [0m] Started [0;1;39mReboot and dump vmcore via kexec[0m.
[[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
[[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
[[0;32m OK [0m] Started [0;1;39mJob spooling tools[0m.
[[0;32m OK [0m] Started [0;1;39mPeriodic Command Scheduler[0m.
[[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
Starting [0;1;39mPrint notice about GPLv3 packages[0m...
Starting [0;1;39mIPv6 Pack[ 7.669824] audit: type=1334 audit(1667152342.308:4): prog-id=7 op=LOAD
et Filtering Framework[0m...
Starting [0;1;39mIPv4 P[ 7.681888] audit: type=1334 audit(1667152342.320:5): prog-id=8 op=LOAD
acket Filtering Framework[0m...
[[0;32m OK [0m] Started [0;1;39mirqbalance daemon[0m.
Starting [0;1;39mTelephony service[0m...
Starting [0;1;39mrc.pvr.service[0m...
Starting [0;1;39mLogin Service[0m...
[[0;32m OK [0m] Started [0;1;39mTEE Supplicant[0m.
[2024-06-03 22:42:15.029]# RECV ASCII>
[[0;32m OK [0m] Started [0;1;39mFile System Check on /dev/mmcblk1p1[0m.
[[0;32m OK [0m] Started [0;1;39mIPv6 Packet Filtering Framework[0m.
[[0;32m OK [0m] Started [0;1;39mIPv4 Packet Filtering Framework[0m.
[[0;32m OK [0m] Started [0;1;39mrc.pvr.service[0m.
[[0;32m OK [0m] Started [0;1;39mTelephony service[0m.
[[0;32m OK [0m] Reached target [0;1;39mNetwork (Pre)[0m.
Mounting [0;1;39m/run/media/mmcblk1p1[0m...
Starting [0;1;39mNetwork Service[0m...
Starting [0;1;39mweston.service[0m...
[2024-06-03 22:42:15.167]# RECV ASCII>
[[0;32m OK [0m] Started [0;1;39mLogin Service[0m.
[[0;32m OK [0m] Mounted [0;1;39m/run/media/mmcblk1p1[0m.
[[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
[ 8.094204] am65-cpsw-nuss c200000.ethernet eth1: PHY [c200f00.mdio:00] driver [TI DP83867] (irq=POLL)
[ 8.106413] am65-cpsw-nuss c200000.ethernet eth1: configuring for phy/rgmii-rxid link mode
Starting [0;1;39mWait for Network to be Configured[0m...
Starting [0;1;39mNetwork Name Resolution[0m...
[ 8.135928] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL)
[ 8.147823] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
[2024-06-03 22:42:15.286]# RECV ASCII>
[[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
[[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
[[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
Starting [0;1;39mAvahi mDNS/DNS-SD Stack[0m...
Starting [0;1;39mEnable and configure wl18xx bluetooth stack[0m...
[[0;32m OK [0m] Started [0;1;39mNFS status monitor for NFSv2/3 locking.[0m.
Starting [0;1;39mSimple Network Ma鈥nt Protocol (SNMP) Daemon.[0m...
Starting [0;1;39mPermit User Sessions[0m...
[[0;32m OK [0m] Started [0;1;39mEnable and configure wl18xx bluetooth stack[0m.
[[0;32m OK [0m] Started [0;1;39mPermit User Sessions[0m.
[[0;32m OK [0m] Started [0;1;39mAvahi mDNS/DNS-SD Stack[0m.
[[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS2[0m.
[[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
Starting [0;1;39mSynchronize System and HW cl
[2024-06-03 22:42:15.337]# RECV ASCII>
ocks[0m...
[[0;32m OK [0m] Started [0;1;39mSynchronize System and HW clocks[0m.
[2024-06-03 22:42:15.614]# RECV ASCII>
[[0;32m OK [0m] Started [0;1;39mSimple Network Man鈥ment Protocol (SNMP) Daemon.[0m.
[2024-06-03 22:42:16.502]# RECV ASCII>
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
autoconf
bash-dev
bash
bc
binutils
cifs-utils
coreutils-stdbuf
coreutils
cpio
cpp-symlinks
cpp
dosfstools
elfutils
g++-symlinks
g++
gawk
gcc-symlinks
gcc
gdb
gdbserver
gettext
glmark2
gstreamer1.0-libav-dev
gstreamer1.0-libav
gzip
less
libasm1
libbfd
libdw1
libelf1
libgdbm-compat4
libgdbm-dev
libgdbm6
libgettextlib
libgettextsrc
libgmp-dev
libgmp10
libgmpxx4
libidn2-0
libidn2-dev
libmpc3
libmpfr6
libreadline-dev
libreadline8
libunistring-dev
libunistring2
m4-dev
m4
make
nettle-dev
nettle
parted
python3-rfc3987
python3-strict-rfc3339
tar
which
zeromq
If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution. This can be done using
the opkg remove command.
[2024-06-03 22:42:16.596]# RECV ASCII>
i.e.:
opkg remove <package>
Where <package> is the name printed in the list above
NOTE: If the package is a dependency of another package you
will be notified of the dependent packages. You should
use the --force-removal-of-dependent-packages option to
also remove the dependent packages as well
***************************************************************
***************************************************************
[[0;32m OK [0m] Started [0;1;39mPrint notice about GPLv3 packages[0m.
[2024-06-03 22:42:17.508]# RECV ASCII>
[[0;32m OK [0m] Started [0;1;39mweston.service[0m.
[2024-06-03 22:42:17.570]# RECV ASCII>
Starting [0;1;39mtelnetd.service[0m...
[[0;32m OK [0m] Started [0;1;39mtelnetd.service[0m.
[2024-06-03 22:42:20.181]# RECV ASCII>
_____ _____ _ _
| _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
| | _| .'| . | . | | __| _| . | | | -_| _| _|
|__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
|___| |___|
Arago Project j784s4-evm ttyS2
Arago 2021.09 j784s4-evm ttyS2
j784s4-evm login:
[2024-06-03 22:42:40.962]# RECV ASCII>
Hi,
When the Boot Application is operating in DDR, it indicates that it is functioning within the Main Domain. It is important to note that any BIST assessments that may affect the overall functionality of the Main Domain cannot be executed from the Boot App. This precaution is necessary to prevent potential corruption of the Boot App itself.
The below PBIST tests must therefore be excluded from Boot App as they should be followed by a Main Domain reset before starting the Boot App.
In the case of the board booting in SD or eMMC boot mode, caution should be exercised when running the following tests, as they impact the SD/eMMC drivers:
Please comment these instances and perform testing as shown in the patch below:
diff -ru sdl_baseline/examples/bist/bist.c sdl/examples/bist/bist.c
--- sdl_baseline/examples/bist/bist.c 2024-01-12 06:08:21.398350632 -0800
+++ sdl/examples/bist/bist.c 2024-01-20 09:08:46.101244213 -0800
@@ -295,6 +295,31 @@
{
continue;
}
+ /* Main Infra0/1, NAVSS and MSMC should not be run, if Boot App is running in DDR */
+ if((i==7)|| (i==2)||(i==6)||(i==25))
+ {
+ continue;
+ }
+ /* HC has MMCSD in Auxiallary list*/
+ if(i==9)
+ {
+ continue;
+ }
+ /* Codecs are impacting QNX SDMMC driver */
+ if ((i==12) || (i==1))
+ {
+ continue;
+ }
+ /* DSS is impacting QNX SDMMC driver */
+ if (i==4)
+ {
+ continue;
+ }
+ /* A72 affects Linux boot */
+ if ((i==13)|| (i==14)||(i==15)||(i==16))
+ {
+ continue;
+ }
#endif
/*MCU instances are not supported for neg and pos test,
So skipped according to the pbist_first_boot_stage array sequence */
@@ -350,6 +375,31 @@
{
continue;
}
+ /* Main Infra0/1, NAVSS and MSMC should not be run, if Boot App is running in DDR */
+ if((i==7)|| (i==2)||(i==6)||(i==25))
+ {
+ continue;
+ }
+ /* HC has MMCSD in Auxiallary list*/
+ if(i==9)
+ {
+ continue;
+ }
+ /* Codecs are impacting QNX SDMMC driver */
+ if ((i==12) || (i==1))
+ {
+ continue;
+ }
+ /* DSS is impacting QNX SDMMC driver */
+ if (i==4)
+ {
+ continue;
+ }
+ /* A72 affects Linux boot */
+ if ((i==13)|| (i==14)||(i==15)||(i==16))
+ {
+ continue;
+ }
#endif
/*MCU instances are not supported for neg and pos test,
So skipped according to the pbist_first_boot_stage array sequence */
@@ -395,6 +445,32 @@
#if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4)
for (i = 0; i < num_pbists_per_boot_stage[j]; i++)
{
+
+ /* Main Infra0/1, NAVSS and MSMC should not be run, if Boot App is running in DDR */
+ if((i==7)|| (i==2)||(i==6)||(i==25))
+ {
+ continue;
+ }
+ /* HC has MMCSD in Auxiallary list*/
+ if(i==9)
+ {
+ continue;
+ }
+ /* Codecs are impacting QNX SDMMC driver */
+ if ((i==12) || (i==1))
+ {
+ continue;
+ }
+ /* DSS is impacting QNX SDMMC driver */
+ if (i==4)
+ {
+ continue;
+ }
+ /* A72 affects Linux boot */
+ if ((i==13)|| (i==14)||(i==15)||(i==16))
+ {
+ continue;
+ }
/* Run test on selected instance */
testResult = PBIST_runTest(pbist_array[i], (uint8_t)PBIST_TEST_ROM);
diff -ru sdl_baseline/examples/bist/pbist_utils.c sdl/examples/bist/pbist_utils.c
--- sdl_baseline/examples/bist/pbist_utils.c 2024-01-12 06:08:21.398350632 -0800
+++ sdl/examples/bist/pbist_utils.c 2024-01-15 09:05:48.365366685 -0800
@@ -535,14 +535,13 @@
{
#if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4)
CSL_ErrType_t status;
- int32_t retValue = 0;
+
/* Add firewall entry to gain access to CLEC registers */
status = PBIST_setFirewall();
if (status != CSL_PASS)
{
UART_printf( " PBIST_setFirewall failed \n");
- retValue = -1;
}
return status;
@@ -1384,7 +1383,7 @@
UART_printf(" Secondary core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].secCoreName);
#endif
- status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecProcId,
+ status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
@@ -1403,7 +1402,7 @@
UART_printf(" Third core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].thCoreName);
#endif
- status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThProcId,
+ status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
@@ -1422,7 +1421,7 @@
UART_printf(" Third core: Taking out of local reset the core %s \n",
PBIST_TestHandleArray[instanceId].foCoreName);
#endif
- status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoProcId,
+ status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoDeviceId,
0x0, /* Local Reset de-asserted */
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != SDL_PASS)
Regards,
Josiitaa
Hi Josiita,
Does this patch ignore the BIST? I migrated it with including BIST Patch into SDK. I can see the linux boot log by UART, but not to see the BIST log by MCU UART.
Thanks
Dengkuan
Hi Dengkuan,
Yes, you will have to use this patch additional to the BIST patch previously shared.
Please find below the patch for integration of BIST with SBL Boot Application on J784s4 SDK 9.1
Regards,
Josiitaa
Hi Josiitaa，
I migrated two patches including BIST and this. I can see the linux boot log by UART, but not to see the BIST log by MCU UART.
Hi Dengkuan,
I have tested using both these patches and I am able to see both the BIST logs and the Linux logs. Can you share your patch so I can compare?
Regards,
Josiitaa