TMDS64EVM: About the two GPIO input interrupts

Kiyomasa Imaizumi

Part Number: TMDS64EVM
Other Parts Discussed in Thread: SYSCONFIG

Hello TI support team.

I am trying GPIO input interrupt with the CR5 sample below.
gpio_input_interrupt_am64x-evm_r5fss0-0_nortos_ti-arm-clang

I am using the SDK mcu_plus_sdk_am64x_09_00_00_35.

The number of GPIO inputs has been increased to two.
Interrupts for ROUTER7 and ROUTER6 are set respectively in sysconfig.

However, when I performed step execution, an error occurred in Sciclient_gpioIrqSet as shown below.
The second Sciclient_rmIrqSet returns 17.

static void Sciclient_gpioIrqSet(void)
{
    int32_t                             retVal;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO0;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO0 + GPIO_GET_BANK_INDEX(53);
    rmIrqReq.dst_id                 = TISCI_DEV_R5FSS0_CORE0;
    rmIrqReq.dst_host_irq           = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_7;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
        DebugP_log("[Error] Sciclient event config failed!!!\r\n");
        DebugP_assert(FALSE);
    }
    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO0;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO0 + GPIO_GET_BANK_INDEX(58);
    rmIrqReq.dst_id                 = TISCI_DEV_R5FSS0_CORE0;
    rmIrqReq.dst_host_irq           = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_6;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);　---> retVal is 17 and error occured.
    if(0 != retVal)
    {
        DebugP_log("[Error] Sciclient event config failed!!!\r\n");
        DebugP_assert(FALSE);
    }
    return;
}

Please tell me any solution.
I will attach the project.

6864.gpio_input_interrupt_am64x-evm_r5fss0-0_nortos_ti-arm-clang.zip

Best regards,
Kiyomasa Imaizumi.

over 1 year ago

0 Kiyomasa Imaizumi over 1 year ago

Intellectual 850 points

Hello TI support team.

In Sciclient_rmProgramInterruptRoute, the following r returned -1.
r = Sciclient_rmIrqFindRoute(&cfg);

I wrote that Sciclient_rmIrqSet returns 17, but it is -1 incorrectly.

I also tried the SDK with mcu_plus_sdk_am64x_09_01_00_41, but the error was the same.

Best regards,
Kiyomasa Imaizumi.

0 Tushar Thakur over 1 year ago in reply to Kiyomasa Imaizumi

TI__Guru 57308 points

Hello Kiyomasa,

Thanks for reaching out to Texas Instruments E2E support forum.

Kiyomasa Imaizumi said:
Please tell me any solution.
I will attach the project.

I can see in the attached project, you are configuring the two pins of same GPIO bank to different router. Because of this configuration you are seeing the above issue.

The Pin #53 and #58 belongs to the same GPIO Bank which can only be routed to single router (i.e either Router output 6 or 7).

If you want to route the interrupts for two pins to different routers, you can configure it as Pin interrupt instead of Bank interrupt.

Please find the below attached project which configures the GPIO interrupt as PIN type instead of BANK Type.

Project - gpio_input_interrupt_am64x_evm_r5fss0_0_nortos_ti_arm_clang.zip

Regards,

Tushar

0 Kiyomasa Imaizumi over 1 year ago in reply to Tushar Thakur

Intellectual 850 points

Hello Tushar Thakur.

Thank you for your reply.

How would I configure my sysconfig to route both pins #53 and #58 to a single router?

As shown in the image below, I get an error when I set it to the same router.

Best regards,

Kiyomasa Imaizumi.

+1 Tushar Thakur over 1 year ago in reply to Kiyomasa Imaizumi

TI__Guru 57308 points

Hello Kiyomasa,

Kiyomasa Imaizumi said:
As shown in the image below, I get an error when I set it to the same router.

Yes, This error is expected. From the sysconfig view you cannot configure a single router for two different GPIO Pins or Banks.

The pin #53 and #58 belongs to the same bank(i.e. GPIO_BANK_3). So you only need to configure either Pin #53 or #58 if the interrupt is Bank type.

After configuring the Bank interrupt, any pins from the same GPIO bank can generate interrupts.

Please refer to Table 12-111. GPIO I/O Signals of TRM for more info.

Please refer below screenshot.

Regards,

Tushar

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TMDS64EVM: About the two GPIO input interrupts