Hi, I'm troubleshooting the following issues
1. environment
- AM5728, using MPU (ARM Cortex-A15 Core 1EA) and PCIE Controller
- 2 processes are reading/writing to OCMC-RAM via L3_MAIN Interconnet path
- 2 Processes Supplemental Description
1) MPU (ARM Cortex-A15 Core) → Data Read Only
2) PCIE Controller (mounted in PCIe slot of PC Main Board and accessed by device driver) → Data Write/Read
2. Issue Phenomenon
Address: 0x40468000
Size: 786Byte
- PCIE Controller writes data of size 786Byte to OCMC-RAM on the PCIE Controller side.
- Calling Cache_inv (ptr, size, Cache_Type_ALLD, TRUE) function on MPU side → I think this action initializes the cache (L1,L2) data and reads the data from OCMC-RAM and updates it to the cache.
When I check the cache data in the above situation, the data value is different from the data value written by the PCIE Controller.
I would appreciate any advice on what I should do and what I should check to solve the problem.
Thank you.
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