• State TI Thinks Resolved
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 101 subscribers
  • Views 706 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PROCESSOR-SDK-J721S2: Is it possible to have a shared memory(DDR) cached between A72 and R5F and do we have a example for it.

Ramakrishnan Venkatraman
Intellectual 985 points

Part Number: PROCESSOR-SDK-J721S2

Is it possible to have a shared memory(DDR) cached between A72 and R5F and do we have a example for it. 

  • 0
    TI__Guru*** 128121 points

    If the R5 needs to share data with the A72, the R5 S/W needs to do R5-side cache maintenance as a producer of the data, but the A72 will not need to do anything special as a consumer.

    For the reverse direction, the A72 accesses to R5, these accesses participate in the coherency protocol and MSMC maintains a snoop cache which will be consulted when the R5 access passes through MSMC.  For coherency 'inner sharable' is the required setting for ARMv8 (A72 in this case) based systems.

  • 0 in reply to KB
    Intellectual 985 points

    Thanks. Do we have any example to check how this can be implemented, 

  • 0 in reply to Ramakrishnan Venkatraman
    Intellectual 985 points

    Kindly let me know if we have an update on this request. Thanks

  • 0 in reply to KB
    Expert 1320 points

    Hi KB,

    1) 

    KB said:
    A72 will not need to do anything special as a consumer.

    -> is it a scenario that only R5F will write the cached shared memory and on a72 side, it will only read the memory but never write it? if yes, then what's the "cache mantenance" R5F should do? and  how to maintain the cache coherency on a72?

    2)

    KB said:
    For the reverse direction, the A72 accesses to R5, these accesses participate in the coherency protocol and MSMC maintains a snoop cache

    -> do we need special configuration for this? and is this the scenario that a72 write the cached shared memory and R5F only read it?

  • 0 in reply to hua SHEN
    TI__Guru*** 128121 points

    Hi,

    (1) The A72 cores data caches, MSMC SRAM, DDR, and other SoC traffic (DMA, R5) support full coherency with A72 caches managed by HW. 

    The R5 cores caches (L1D) are not kept coherent by HW, so SW managed coherency is required for all data shared with other R5's, A72, or DMA.

    (2) As per above response, on the A72, the coherency for the mapped memory must be 'inner sharable' as is the required setting for ARMv8 (A72 in this case) based systems.

  • 0 in reply to KB
    Expert 1320 points

    Hi KB，

    a question:

    KB said:
    these accesses participate in the coherency protocol and MSMC maintains a snoop cache which will be consulted when the R5 access passes through MSMC

    -> from this, seems there's a HW mechanism for the coherency,  while you say R5 core coherency should be managed by SW. so if A72 is the producer, could you explain how to manage the coherency?

  • 0 in reply to hua SHEN
    TI__Guru*** 128121 points

    On the A72 side, when creating the memory map, it must be created/mapped as 'inner shareable'.  In all likely hood this would be in place already.

    The TI Shared Memory Allocator, allocates memory which is shared between the A72 vs R5, which is used by the TI OpenVx framework.  The shared memory allocator does necessarily need to be used, it is just an example framework.

    Regards,

    kb