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TMS320C6748: The data processing algorithm interface caused the timer Timer2 interrupt (INT5) to fail to respond, UART2 interrupt (INT4) but can respond in a timely manner

Part Number: TMS320C6748

I am currently using DSP TMS320C6748, bare metal, and the main program is AD data acquisition and processing, UART2 interrupt priority 4, Timer2 interrupt priority 5.
Actual testing situation: When algorithm interfaces (mainly filtering and other data processing interfaces) exist (not annotated), UART2 interrupt response rate reaches 99%, Timer2 interrupts are only 20% or less.
When algorithm interfaces (mainly filtering and other data processing interfaces) do not exist (annotated), the response rate is 100%.
The running time of the algorithm interface is 200ms, and the timer Timer2 cycle is set to 4ms, 10ms, 100ms, and 500ms, all of which have been tested.
The question is: even if the CPU occupies a lot of resources during algorithm processing, after the 200ms algorithm interface ends and there is enough idle time (greater than 700ms), the timer should respond to interrupts. Actual testing shows that Timer2 did not respond in a timely manner, but UART2 can basically respond under the same conditions.
May I ask if your company's technical support team has encountered a similar problem (the main program affects interrupt response), and how should we solve it? Do you have any information for reference