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A problem about DDR3 clock design with TMS320C6670

odzy
Prodigy 120 points

Other Parts Discussed in Thread: CDCE62005, TMS320C6670, CDCE62002

Hi all! I am designing a board with a TMS320C6670 in it. And I found that in the TMS320C6670, the DDR3 clock is generated by a CDCE62002, whose ref clk is come from the CDCE62005, but I am wondering why is the clock generated by the CDCE62005 directly? Does the DDR3 clock need to be distributed alone or sth. else? Thx!

  • 0
    TI__Mastermind 30825 points

    The DDR3 Clock does not need to be distributed alone.  I'm not sure exactly why Advantech did it this way, but if you look at the TMDXEVM6678L EVM, you'll see where they use 2 CDCE62005 w/ one XTAL and (one one of the outputs of the first CDCE62002 as reference to the 2nd CDCE6202.)  The first CDCE62005 provides Core, DDR and Ref to the 2nd CDCE62005.

    As long as the clocking requirements such as jitter requirements are met, you can do it a number of way.

    Best Regards,

    Chad

  • 0
    TI__Mastermind 42545 points

    I am assuming that you are referring to the C6670 EVM which uses a CDCE62002 for the 66.67MHz DDR reference clock and two CDCE62005s for the rest of the clock frequencies.  Note that the CDCE clock generators only have one synthesizer block to create the primary clock frequency as a basis for each of the output frequencies.  The outputs are then divided down from the frequency created by the synthesizer.  The Advantech design team decided that they couldn't easily create the serdes reference clock frequencies and the DDR reference clock frequency from the same primary base clock and choose to use a separate clock generator.