SK-AM69: C7x crash while using L1 memory

Hello TI,

I am using a SK-AM69 Board and the SDK for j784s4 v9.2.0.5.

I boot Linux and program one of the C7120 DSP with a tiny test program using CCS 12.7.

The program calls MATHLIB_exp2() from the mathlib v9.2.0.4. When I link the input buffer into L2 (starting at 0x64800000), everything works fine.

When I use L1 (starting at 0x64E00000) for the input instead, the program somewhere crashes inside the MATHLIB_exp2().

There is no change to the default cache setup. I assume L1 cache is configured as 32 KB and 16 KB is then left over for any data usage, right?

Does anyone have an idea what causes the crash?

Best,

Kim

My tiny test program is as follows:

#include <stdio.h>
#include <cmath>
#include "MATHLIB_lut.h"
#include "mathlib.h"

#define C7X_VECTOR_SIZE_FOR_TEST 8
#pragma DATA_SECTION(".l1data")
float input1_vector[C7X_VECTOR_SIZE_FOR_TEST];
#pragma DATA_SECTION(".l2data")
float outputVector[C7X_VECTOR_SIZE_FOR_TEST];

int main(int argc, char *argv[])
{

    MATHLIB_LUTInit(); // Needed for log, pow, ...

    // Initialize input
    for(int i=0; i<C7X_VECTOR_SIZE_FOR_TEST;i++) {
        input1_vector[i] = 1.f + C7X_VECTOR_SIZE_FOR_TEST/(float)(i+1) + (float)(i+1)/C7X_VECTOR_SIZE_FOR_TEST;
        outputVector[i] = 0.f;
        //printf("input1_vector[%d] = %f\t", i, input1_vector[i]);
    }

    printf("... MATHLIB_exp2 ... \n");

    MATHLIB_exp2(C7X_VECTOR_SIZE_FOR_TEST, input1_vector, outputVector);

    printf("... MATHLIB_exp2 done ... \n");

    return 0;
}

The linker command file looks like this:

--ram_model
-heap  0x210000
-stack 0x60000
--args 0x1000
--diag_suppress=10068 /* "no matching section" */
--cinit_compression=off
-e _c_int00

#define DDR0_ALLOCATED_START  0xA0000000
#define C7X_ALLOCATED_START DDR0_ALLOCATED_START + 0x06000000 // TODO: why sometimes + 0x08000000 (non-RTOS?)

#define C7X_EXT_DATA_BASE   (C7X_ALLOCATED_START + 0x00100000)
#define C7X_MEM_TEXT_BASE   (C7X_ALLOCATED_START + 0x00200000)
#define C7X_MEM_DATA_BASE   (C7X_ALLOCATED_START + 0x00300000)
#define C7X_DDR_SPACE_BASE  (C7X_ALLOCATED_START + 0x00400000)
#define C7X_L2RAM_BASE      (0x64800000)
#define C7X_L1RAM_BASE      (0x64E00000)

MEMORY
{
    DDR0_RESERVED: org = 0x80000000,          len = 0x20000000   /* 512MB Reserved for A72 OS */
    C7X_IPC_D:     org = C7X_ALLOCATED_START, len = 0x00100000   /*  1MB DDR */
    C7X_EXT_D:     org = C7X_EXT_DATA_BASE,   len = 0x00100000   /*  1MB DDR */
    C7X_TEXT:      org = C7X_MEM_TEXT_BASE,   len = 0x00100000   /*  1MB DDR */
    C7X_DATA:      org = C7X_MEM_DATA_BASE,   len = 0x00100000   /*  1MB DDR */
    C7X_DDR_SPACE: org = C7X_DDR_SPACE_BASE,  len = 0x00C00000   /* 12MB DDR */
    C7X_L1RAM      org = C7X_L1RAM_BASE       len = 0x00004000 // 16 KB left while utalizing 32 KB for cache
    C7X_L2RAM      org = C7X_L2RAM_BASE       len = 0x00070000
}

SECTIONS
{
    boot:
    {
      boot.*<boot.oe71>(.text)
    } load > C7X_TEXT ALIGN(0x200000)
    .vecs       >       C7X_DDR_SPACE ALIGN(0x400000)
    .secure_vecs    >   C7X_DDR_SPACE ALIGN(0x200000)
    .text:_c_int00 > C7X_DDR_SPACE ALIGN(0x200000)
    .text       >       C7X_DDR_SPACE ALIGN(0x200000)
    .bss        >       C7X_DDR_SPACE  /* Zero-initialized data */
    .data       >       C7X_DATA  /* Initialized (global and local) data */
    .cinit      >       C7X_DDR_SPACE  /* could be part of const */
    .init_array >       C7X_DDR_SPACE  /* C++ initializations */
    .stack      >       C7X_DDR_SPACE ALIGN(0x2000)
    .args       >       C7X_DDR_SPACE
    .cio        >       C7X_DDR_SPACE
    .const      >       C7X_DDR_SPACE
    .switch     >       C7X_DDR_SPACE /* For exception handling. */
    .sysmem     >       C7X_DDR_SPACE /* heap */
    .l1data     >       C7X_L1RAM // TODO: Fix crash if used
    .l2data     >       C7X_L2RAM
    .c7xabi.extab > C7X_DDR_SPACE
    .c7xabi.exidx > C7X_DDR_SPACE

    GROUP:              >  C7X_DDR_SPACE
    {
        .data.Mmu_tableArray          : type=NOINIT
        .data.Mmu_tableArraySlot      : type=NOINIT
        .data.Mmu_level1Table         : type=NOINIT
        .data.Mmu_tableArray_NS       : type=NOINIT
        .data.Mmu_tableArraySlot_NS   : type=NOINIT
        .data.Mmu_level1Table_NS      : type=NOINIT
    }

    ipc_data_buffer:       > C7X_DDR_SPACE
    .benchmark_buffer:     > C7X_DDR_SPACE ALIGN (32)

    .resource_table: { __RESOURCE_TABLE = .;} > C7X_EXT_D
}