Booting OMAP-L138 (the story is now complete!)

MikeH

Jeff,

(continued from http://e2e.ti.com/support/embedded/f/355/p/89971/327197.aspx#327197)

OK. Now I am to the point where all of my ARM code is working as it should, as well as my actual DSP application code. I need to program these two .out files into my SPI flash.

As stated in an earlier post (thanks Mukul http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/136393/490578.aspx#490578) my ARM initialization code works as expected when programmed (separately) into SPI Flash. However, when I use AISGen to create a combined file for ARM+DSP neither the ARM nor DSP code operates after power-on booting.

I can start a debug session, connect to the ARM and see that the code is properly loaded into the desired shared ram location. However, the ARM program counter is stuck at a point in IRAM (0xFFFD397C) instead of c_int00 (ENTRY POINT SYMBOL: "_c_int00" address: 80008064). If I set the PC to 0x80008064, then hit Run, the ARM program runs properly, confirming that the SPI Flash loaded the ARM code properly. But, after a power-on reset, the ARM is stuck in IRAM.

I can also connect to the DSP and look at its program memory. The code appears to be loaded properly but the DSP is stuck somewhere in DSP/BIOS around TSK_exit. I cannot get the DSP app to run by entering 0xc0000000 into the PC, which is where I have set the HOST1CFG value in the ARM init code (SYSCONFIG->HOST1CFG = (0xC0000000 & 0xFFFFFC00); //DSP boot address @ power-on reset.).

Here is my AISGen cfg file FYI

Boot Mode=SPI1 Flash

Boot Speed=10

Flash Width=0

Flash Timing=3ffffffc

Configure Peripheral=True

Configure PLL0=True

Configure SDRAM=False

Configure PLL1=True

Configure DDR2=True

Configure LPSC=False

Configure Pinmux=True

Enable CRC=False

Specify Entrypoint=False

Enable Sequential Read=False

Use 4.5 Clock Divider=False

Use DDR2 Direct Clock=False

Use mDDR=True

ROM ID=0

Device Type=0

Input Clock Speed=24

Clock Type=0

PLL0 Pre Divider=1

PLL0 Multiplier=25

PLL0 Post Divider=2

PLL0 Div1=1

PLL0 Div3=12

PLL0 Div7=6

PLL1 Multiplier=25

PLL1 Post Divider=2

PLL1 Div1=1

PLL1 Div2=2

PLL1 Div3=3

Entrypoint=0

SDRAM SDBCR=0

SDRAM SDTMR=0

SDRAM SDRSRPDEXIT=0

SDRAM SDRCR=0

DDR2 PHY=c4

DDR2 SDCR=a034622

DDR2 SDCR2=0

DDR2 SDTIMR=1c912a08

DDR2 SDTIMR2=3811c700

DDR2 SDRCR=494

LPSC0 Enable=

LPSC0 Disable=

LPSC0 SyncRst=

LPSC1 Enable=

LPSC1 Disable=

LPSC1 SyncRst=

Pinmux=

App File String=C:\Users\Mike\TI Workspaces\AMX_9-20-11\ARM_init_simple\Debug\ARM_init_simple.out;C:\Users\Mike\TI Workspaces\AMX_9-20-11\DSP_CELT\Debug\DSP_CELT.out

AIS File Name=C:\Users\Mike\TI Workspaces\AMX_9-20-11\ARM_init_simple\Debug\arm+dsp.bin

Any ideas on how to debug this?

over 13 years ago

0 jc-ti over 13 years ago

TI__Mastermind 27585 points

Hi Mike,

As usual we will need the printout from the debug GEL file: http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files

From the PC it looks like the ARM is in an abort loop, so the GEL will tell us what error it encountered.

Jeff

0 MikeH over 13 years ago in reply to jc-ti

Guru 15580 points

Jeff,

The following was obtained by:

1. Boot from SPI Flash.

2. Connect to ARM. Manually run the ARM init program so that the DSP is not being held in reset.

3. Connect to the DSP.

4. Run the GEL debug script.

Here's the output.

C674X_0: GEL Output:

---------------------------------------------

C674X_0: GEL Output: | Device Information |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F

C674X_0: GEL Output: DEV_INFO_01 = 0x00000000

C674X_0: GEL Output: DEV_INFO_02 = 0x0000000C

C674X_0: GEL Output: DEV_INFO_03 = 0x00000032

C674X_0: GEL Output: DEV_INFO_04 = 0x00000000

C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0

C674X_0: GEL Output: DEV_INFO_06 = 0x00000080

C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5337268-20-10-25

C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,7206

C674X_0: GEL Output: -----

C674X_0: GEL Output: DEV_INFO_17 = 0x00030003

C674X_0: GEL Output: DEV_INFO_18 = 0x00000000

C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:

C674X_0: GEL Output: -----

C674X_0: GEL Output: DEV_INFO_20 = 0x30303864

C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B

C674X_0: GEL Output: DEV_INFO_22 = 0x00000000

C674X_0: GEL Output: DEV_INFO_23 = 0x00000000

C674X_0: GEL Output: -----

C674X_0: GEL Output: DEV_INFO_24 = 0x1401900A

C674X_0: GEL Output: DEV_INFO_25 = 0x005170B4

C674X_0: GEL Output: DEV_INFO_06 = 0x00000080

C674X_0: GEL Output: DEV_INFO_26 = 0x384C0002

C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: | BOOTROM Info |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: ROM ID: d800k006

C674X_0: GEL Output: Silicon Revision 2.0

C674X_0: GEL Output: Boot Mode: SPI1 Flash

C674X_0: GEL Output:

ROM Status Code: 0x00000001

Description:C674X_0: GEL Output: DSP was put to sleep

C674X_0: GEL Output:

Program Counter (PC) = 0xC0000000

C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: | Clock Information |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output:

C674X_0: GEL Output: PLLs configured to utilize crystal.

C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2

C674X_0: GEL Output:

C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based

C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware

C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,

C674X_0: GEL Output: and then reload.

C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: | PLL0 Information |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output:

C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz

C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz

C674X_0: GEL Output: PLL0_SYSCLK3 = 25 MHz

C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz

C674X_0: GEL Output: PLL0_SYSCLK5 = 300 MHz

C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz

C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz

C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: | PLL1 Information |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output:

C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz

C674X_0: GEL Output: PLL1_SYSCLK2 = 150 MHz

C674X_0: GEL Output: PLL1_SYSCLK3 = 300 MHz

C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: | PSC0 Information |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output:

C674X_0: GEL Output: State Decoder:

C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)

C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)

C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)

C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)

C674X_0: GEL Output: >3 = Transition in progress

C674X_0: GEL Output:

C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3

C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3

C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 3

C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3

C674X_0: GEL Output: Module 4: SPI 0 STATE = 3

C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 3

C674X_0: GEL Output: Module 6: AINTC STATE = 3

C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3

C674X_0: GEL Output: Module 9: UART 0 STATE = 3

C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3

C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3

C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3

C674X_0: GEL Output: Module 13: PRUSS STATE = 0

C674X_0: GEL Output: Module 14: ARM STATE = 3

C674X_0: GEL Output: Module 15: DSP STATE = 3

C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output: | PSC1 Information |

C674X_0: GEL Output: ---------------------------------------------

C674X_0: GEL Output:

C674X_0: GEL Output: State Decoder:

C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)

C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)

C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)

C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)

C674X_0: GEL Output: >3 = Transition in progress

C674X_0: GEL Output:

C674X_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3

C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 3

C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 3

C674X_0: GEL Output: Module 3: GPIO STATE = 3

C674X_0: GEL Output: Module 4: UHPI STATE = 3

C674X_0: GEL Output: Module 5: EMAC STATE = 3

C674X_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3

C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3

C674X_0: GEL Output: Module 8: SATA STATE = 3

C674X_0: GEL Output: Module 9: VPIF STATE = 3

C674X_0: GEL Output: Module 10: SPI 1 STATE = 3

C674X_0: GEL Output: Module 11: I2C 1 STATE = 3

C674X_0: GEL Output: Module 12: UART 1 STATE = 3

C674X_0: GEL Output: Module 13: UART 2 STATE = 3

C674X_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 3

C674X_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 3

C674X_0: GEL Output: Module 16: LCDC STATE = 3

C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 3

C674X_0: GEL Output: Module 18: MMC/SD 1 STATE = 3

C674X_0: GEL Output: Module 19: UPP STATE = 3

C674X_0: GEL Output: Module 20: eCAP (all) STATE = 3

C674X_0: GEL Output: Module 21: EDMA3 TC2 STATE = 3

C674X_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3

C674X_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3

C674X_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3

C674X_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3

C674X_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3

C674X_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3

C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3

C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

Please let me know if you see anything wrong.

0 jc-ti over 13 years ago in reply to MikeH

TI__Mastermind 27585 points

Mike, run the GEL from the ARM side immediately after connecting before running any code. Thanks,

Jeff

0 MikeH over 13 years ago in reply to jc-ti

Guru 15580 points

Jeff,

jc-ti said:
run the GEL from the ARM side immediately after connecting before running any code

See below:

ARM9_0: GEL Output:

---------------------------------------------

ARM9_0: GEL Output: | Device Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F

ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_02 = 0x0000000C

ARM9_0: GEL Output: DEV_INFO_03 = 0x00000032

ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0

ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080

ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5337268-20-10-25

ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,7206

ARM9_0: GEL Output: -----

ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003

ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:

ARM9_0: GEL Output: -----

ARM9_0: GEL Output: DEV_INFO_20 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_21 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864

ARM9_0: GEL Output: DEV_INFO_23 = 0x3630306B

ARM9_0: GEL Output: -----

ARM9_0: GEL Output: DEV_INFO_24 = 0x1401900A

ARM9_0: GEL Output: DEV_INFO_25 = 0x005170B4

ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080

ARM9_0: GEL Output: DEV_INFO_26 = 0x384C0002

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | BOOTROM Info |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: ROM ID: d800k006

ARM9_0: GEL Output: Silicon Revision 2.0

ARM9_0: GEL Output: Boot Mode: SPI1 Flash

ARM9_0: GEL Output:

ROM Status Code: 0x0000000A

Description:ARM9_0: GEL Output: Invalid AIS sync opcode

ARM9_0: GEL Output:

Program Counter (PC) = 0xFFFD397C

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | Clock Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: PLLs configured to utilize crystal.

ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2

ARM9_0: GEL Output:

ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based

ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware

ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,

ARM9_0: GEL Output: and then reload.

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PLL0 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: PLL0_SYSCLK1 = 300 MHz

ARM9_0: GEL Output: PLL0_SYSCLK2 = 150 MHz

ARM9_0: GEL Output: PLL0_SYSCLK3 = 25 MHz

ARM9_0: GEL Output: PLL0_SYSCLK4 = 75 MHz

ARM9_0: GEL Output: PLL0_SYSCLK5 = 300 MHz

ARM9_0: GEL Output: PLL0_SYSCLK6 = 300 MHz

ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PLL1 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz

ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz

ARM9_0: GEL Output: PLL1_SYSCLK3 = 300 MHz

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PSC0 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: State Decoder:

ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)

ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)

ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)

ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)

ARM9_0: GEL Output: >3 = Transition in progress

ARM9_0: GEL Output:

ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0

ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0

ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0

ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 0

ARM9_0: GEL Output: Module 4: SPI 0 STATE = 0

ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 0

ARM9_0: GEL Output: Module 6: AINTC STATE = 3

ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3

ARM9_0: GEL Output: Module 9: UART 0 STATE = 0

ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3

ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3

ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3

ARM9_0: GEL Output: Module 13: PRUSS STATE = 0

ARM9_0: GEL Output: Module 14: ARM STATE = 3

ARM9_0: GEL Output: Module 15: DSP STATE = 0

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PSC1 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: State Decoder:

ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)

ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)

ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)

ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)

ARM9_0: GEL Output: >3 = Transition in progress

ARM9_0: GEL Output:

ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0

ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 0

ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 0

ARM9_0: GEL Output: Module 3: GPIO STATE = 0

ARM9_0: GEL Output: Module 4: UHPI STATE = 0

ARM9_0: GEL Output: Module 5: EMAC STATE = 0

ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3

ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0

ARM9_0: GEL Output: Module 8: SATA STATE = 0

ARM9_0: GEL Output: Module 9: VPIF STATE = 0

ARM9_0: GEL Output: Module 10: SPI 1 STATE = 3

ARM9_0: GEL Output: Module 11: I2C 1 STATE = 0

ARM9_0: GEL Output: Module 12: UART 1 STATE = 0

ARM9_0: GEL Output: Module 13: UART 2 STATE = 0

ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0

ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0

ARM9_0: GEL Output: Module 16: LCDC STATE = 0

ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 0

ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 0

ARM9_0: GEL Output: Module 19: UPP STATE = 0

ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 0

ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0

ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3

ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3

ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3

ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3

ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3

ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3

ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3

ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

0 jc-ti over 13 years ago in reply to MikeH

TI__Mastermind 27585 points

The error code indicates that it read back unexpected data from the AIS image. Assuming the flashed image itself is correct it might be a read problem.

Also it looks like you are using d800k006 (PG2.0) but your AIS config is still set to d800k002 (PG1.0). Can you regenerate with d800k006 and try again?

Jeff

0 MikeH over 13 years ago in reply to jc-ti

Guru 15580 points

Jeff,

Looks like the same issue (read error). However, if I program only the ARM application, things work OK.

ARM9_0: GEL Output:

---------------------------------------------

ARM9_0: GEL Output: | Device Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F

ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_02 = 0x0000000C

ARM9_0: GEL Output: DEV_INFO_03 = 0x00000032

ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0

ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080

ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5337268-20-10-25

ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,7206

ARM9_0: GEL Output: -----

ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003

ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000

ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:

ARM9_0: GEL Output: -----

ARM9_0: GEL Output: DEV_INFO_20 = 0x30303864

ARM9_0: GEL Output: DEV_INFO_21 = 0x3630306B

ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864

ARM9_0: GEL Output: DEV_INFO_23 = 0x3630306B

ARM9_0: GEL Output: -----

ARM9_0: GEL Output: DEV_INFO_24 = 0x1401900A

ARM9_0: GEL Output: DEV_INFO_25 = 0x005170B4

ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080

ARM9_0: GEL Output: DEV_INFO_26 = 0x384C0002

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | BOOTROM Info |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: ROM ID: d800k006

ARM9_0: GEL Output: Silicon Revision 2.0

ARM9_0: GEL Output: Boot Mode: SPI1 Flash

ARM9_0: GEL Output:

ROM Status Code: 0x0000000A

Description:ARM9_0: GEL Output: Invalid AIS sync opcode

ARM9_0: GEL Output:

Program Counter (PC) = 0xFFFD397C

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | Clock Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: PLLs configured to utilize crystal.

ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2

ARM9_0: GEL Output:

ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based

ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware

ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,

ARM9_0: GEL Output: and then reload.

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PLL0 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: PLL0_SYSCLK1 = 300 MHz

ARM9_0: GEL Output: PLL0_SYSCLK2 = 150 MHz

ARM9_0: GEL Output: PLL0_SYSCLK3 = 25 MHz

ARM9_0: GEL Output: PLL0_SYSCLK4 = 75 MHz

ARM9_0: GEL Output: PLL0_SYSCLK5 = 300 MHz

ARM9_0: GEL Output: PLL0_SYSCLK6 = 300 MHz

ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PLL1 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz

ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz

ARM9_0: GEL Output: PLL1_SYSCLK3 = 300 MHz

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PSC0 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: State Decoder:

ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)

ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)

ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)

ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)

ARM9_0: GEL Output: >3 = Transition in progress

ARM9_0: GEL Output:

ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0

ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0

ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0

ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 0

ARM9_0: GEL Output: Module 4: SPI 0 STATE = 0

ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 0

ARM9_0: GEL Output: Module 6: AINTC STATE = 3

ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3

ARM9_0: GEL Output: Module 9: UART 0 STATE = 0

ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3

ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3

ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3

ARM9_0: GEL Output: Module 13: PRUSS STATE = 0

ARM9_0: GEL Output: Module 14: ARM STATE = 3

ARM9_0: GEL Output: Module 15: DSP STATE = 3

ARM9_0: GEL Output:

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output: | PSC1 Information |

ARM9_0: GEL Output: ---------------------------------------------

ARM9_0: GEL Output:

ARM9_0: GEL Output: State Decoder:

ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)

ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)

ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)

ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)

ARM9_0: GEL Output: >3 = Transition in progress

ARM9_0: GEL Output:

ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0

ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 0

ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 0

ARM9_0: GEL Output: Module 3: GPIO STATE = 0

ARM9_0: GEL Output: Module 4: UHPI STATE = 0

ARM9_0: GEL Output: Module 5: EMAC STATE = 0

ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3

ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0

ARM9_0: GEL Output: Module 8: SATA STATE = 0

ARM9_0: GEL Output: Module 9: VPIF STATE = 0

ARM9_0: GEL Output: Module 10: SPI 1 STATE = 3

ARM9_0: GEL Output: Module 11: I2C 1 STATE = 0

ARM9_0: GEL Output: Module 12: UART 1 STATE = 0

ARM9_0: GEL Output: Module 13: UART 2 STATE = 0

ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0

ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0

ARM9_0: GEL Output: Module 16: LCDC STATE = 0

ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 0

ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 0

ARM9_0: GEL Output: Module 19: UPP STATE = 0

ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 0

ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0

ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3

ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3

ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3

ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3

ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3

ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3

ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3

ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3

0 MikeH over 13 years ago in reply to MikeH

Guru 15580 points

Jeff,

Would you also take a look at my config file. Am I turning on all of the requried PSC's?

Boot Mode=SPI1 Flash

Boot Speed=2

Flash Width=0

Flash Timing=3ffffffc

Configure Peripheral=True

Configure PLL0=True

Configure SDRAM=False

Configure PLL1=True

Configure DDR2=True

Configure LPSC=True

Configure Pinmux=True

Enable CRC=False

Specify Entrypoint=False

Enable Sequential Read=False

Use 4.5 Clock Divider=False

Use DDR2 Direct Clock=False

Use mDDR=True

ROM ID=2

Device Type=0

Input Clock Speed=24

Clock Type=0

PLL0 Pre Divider=1

PLL0 Multiplier=25

PLL0 Post Divider=2

PLL0 Div1=1

PLL0 Div3=12

PLL0 Div7=6

PLL1 Multiplier=25

PLL1 Post Divider=2

PLL1 Div1=1

PLL1 Div2=2

PLL1 Div3=3

Entrypoint=0

SDRAM SDBCR=0

SDRAM SDTMR=0

SDRAM SDRSRPDEXIT=0

SDRAM SDRCR=0

DDR2 PHY=c4

DDR2 SDCR=a034622

DDR2 SDCR2=0

DDR2 SDTIMR=1c912a08

DDR2 SDTIMR2=3811c700

DDR2 SDRCR=494

LPSC0 Enable=15+

LPSC0 Disable=

LPSC0 SyncRst=

LPSC1 Enable=

LPSC1 Disable=

LPSC1 SyncRst=

Pinmux=

App File String=C:\Users\Mike\TI Workspaces\AMX_9-20-11\ARM_init_simple\Debug\ARM_init_simple.out;C:\Users\Mike\TI Workspaces\AMX_9-20-11\DSP_CELT\Debug\DSP_CELT.out

AIS File Name=C:\Users\Mike\TI Workspaces\AMX_9-20-11\ARM_init_simple\Debug\arm+dsp.bin

0 MikeH over 13 years ago in reply to MikeH

Guru 15580 points

I just want to take a moment to thank Jeff and friends for their "above and beyond" support on getting this thing working! We've spent the last several days going back and forth debugging what turned out to be a problem with my SPI Flash code (did not write the complete image file).

Thanks again Jeff!

I can now close out this saga and move on.

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Booting OMAP-L138 (the story is now complete!)