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PROCESSOR-SDK-J784S4: Request for communication interface between MCU R5F and Main R5F.

Part Number: PROCESSOR-SDK-J784S4


Tool/software:

Kindly let me know if there is a communication interface available between MCU R5F and Main R5F directly through SCI Interface or it has to be routed through A72 in Main domain.

Even if it is not SCI interface, do we have any other interfaces between MCU R5F and Main R5F that can registered through some SW interrupt so that it can be invoked instantly. 

Thanks a lot in advance, 

  • Hello,

    Are you talking about SCI client calls ? We have IPC mechanism to communicate between cores.Can you please tell me what is your intent ? so i can suggest you better.

    Regards

    Tarun Mukesh

  • Hi Tarun, 

    I am trying to put a design for timesync for overall SoC. I see there a CPTS module available on the SoC. So wanted to understand how the synchronization shall be achieved b/w MCU and main domain with the external PTP timestamp with this module thereby reducing sw handling in this synchronization. 

  • Also could you please share the HW manual with the list of registers for J784S4. 

  • Hi,

    Also could you please share the HW manual with the list of registers for J784S4. 

    Please refer to SOC Page, has TRM which has H/W Manual PDF and Register details in Excel file.

    So wanted to understand how the synchronization shall be achieved b/w MCU and main domain with the external PTP timestamp with this module thereby reducing sw handling in this synchronization. 

    J784S4 has support for EthFw application for CPSW9G, which supports gPTP stack on RTOS SDK from PDK and sync with external PTP.
    Also, you can use Native Linux Driver for CPSW2G/CPSW9G ,which supports gPTP from Linux kernel and sync with external PTP.

    CPSW2G and CPSW9G has its own CPTS module, using this it will sync with external PTP.

    We don't have s/w support for Multi-core time sync.

    Ideally other cores needs to use GTC timer and maintain the time difference from CPTS and GTC by getting the CPTS time using push events and time sync route.
    Please refer to time sync design reference from PDK Trainings.

    Few of customer are using GTC and maintaining shared memory across all cores and updating the synchronized time adjusted to GTC so all other cores will read the same time in shared memory.

    Note:
    We don't have support for Multi-core time sync from TI SDK.

    Best Regards,
    Sudheer

  • Thanks Sudheer for the detailed explanation. I have two queries from the PDK trainings. 

    1) The synchronized time in R5F main domain is computed using below formula. 

    = ∗ + C

    – Synchronized Time (CPTS time) – Rate ratio – Local Timer Value – Constant value

    wanted to understand how 'r' is computed using two continuous CPTS push events and same way how C is computed. 

    2) I don't have Ethernet connected to main domain(both A72 and R5F don't have it). In that case whether MCU R5F(since it receives the PTP time) can update the GTC ticks/counters after the synchronizing with vehicle time and thereby send CPTS push notifications to the Main domain R5F and A72 and with that whether overall TDA4x system would be synchronized. Kindly let me know. 

  • Sorry formula is as below.  = ∗ + C

  • Also please let me know how to "Register the Remote Timer with the CPTS timer" through remote config client examples. 

  • Hi,

    Multi-core time sync is not yet available from TI SDK.
    Above PDF will be reference design, how it may achieve.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    From the PDK reference would the below point still work in R5F through remote config client(Main r5f) and emote config server(MCU R5F). 

    I don't have Ethernet connected to main domain(both A72 and R5F don't have it). In that case whether MCU R5F(since it receives the PTP time) can update the GTC ticks/counters after the synchronizing with vehicle time and thereby send CPTS push notifications to the Main domain R5F and A72 and with that whether overall TDA4x system would be synchronized. Kindly let me know. 

  • Hi,

    Are you using MCAL Eth Driver for MCU_CPSW2G?
    If so, we don't have support for CPTS modules configuration and timesync with External network via PTP.

    TI SDK has PTP support via EthFw and Enet example on MCU2_0 (Main R5F).

    From the PDK reference would the below point still work in R5F through remote config client(Main r5f) and emote config server(MCU R5F). 

    Remote client on Main R5F we have but Server on MCU R5F is not supported.
    Ethfw server only support on MCU2_0 (It is S/W Limitation).

    In that case whether MCU R5F(since it receives the PTP time) can update the GTC ticks/counters after the synchronizing with vehicle time and thereby send CPTS push notifications to the Main domain R5F and A72 and with that whether overall TDA4x system would be synchronized. Kindly let me know

    GTC is common for all cores, once you have enabled GTC and all cores can read the GTC counter value.

    Few of customer are using GTC and maintaining shared memory across all cores and updating the synchronized time adjusted to GTC so all other cores will read the same time in shared memory.

    Above I have informed is maintain shared memory for all cores, PTP running core adjust GTC with PTP and maintain the adjustment value in shared memory and update regurarly.

    Other cores reads the GTC value and add this adjustment in shared memory so it will equivalent of PTP time.

    Note:
    Above information will be for your reference. TI SDK does not support Multi-core time-sync.


    Best Regards,
    Sudheer