AM6442: PCIe cannot link-up

Hideaki Matsumoto

Genius 9640 points

Part Number: AM6442
Other Parts Discussed in Thread: TMDS64EVM, AM2434

Tool/software:

Hi,

My customer is now evaluating PCIe on AM64x, but it cannot be linked up. Could you please give them something advice.

< HW Environments >

Root-Complex : EVM #1 (TMDS64EVM)

End-point : EVM #2 (TMDS64EVM )

RC (EVM #1) <---- (Card Edge Cable) ----> EP (EVM #2)

Card Edge Cable 8KJ2-0743-0250 (64 Position PCIe x4 Card Edge to Card Edge 0.820') is modified to connect A16/A17 of RC on EVM #1 to B14/B15 of EP on EVM #2, and each terminal is inserted into J27 connector of each EVM.

< Example Software >

They’re using the Example Projects in the folder of “example / drivers / pcie /pcie_benchmark” in the mcu_plus_sdk_am64x_09_01_00_41.

< Evaluation Procedure >

EP (EVM #2) starts-up at first.
RC (EVM #1) starts-up immediately after starting-up EVM #2.

< Results >

It seems that PCIe cannot succeed the link-up.

Both RC and EP displayed “MAIN_Cortex_R5_0_0:AM2434_ALV” in the console output.

They dumped PCIe registers by stopping RC operation after 20 seconds.

EP RC
-----------------------------------------------------------------------------------------

0x0F100000 :PCIE0_revid :0x68141900 : 0x68141900

0x0F100004 :PCIE0_cmd_status :0x00000001 : 0x00000001

0x0F100008 :PCIE0_rstcmd :0x00000000 : 0x00000000

0x0F10000C :PCIE0_initcfg :0x01C41FFC : 0x01C41FFC

0x0F100014 :PCIE0_linkstatus :0x01000000 : 0x03000001

Could you please give them any advice to connect PCIe or should they check something ?

They wonder

PCIe cable should be something special ?

some more settings are needed on RC side ?

any program modification should be needed on RC side ?

because EP seems to have no issue from the following another evaluation.

When they connected EP (EVM #2) to other SoC board (PCIe Gen1), then “Device in EP mode” was output to the Console on EVM #2. It looks success to link-up.

RC (Other SoC Board) <---- (PCIe supported Cable) ----> EP (TMDS64EVM #2)

When they read the address 0x0F10_0014 by CCS on EP (EVM #2) after stopping RC (Other SoC Board)

0x10000103

LTSSM_STATE = 10h – L0
LINK_STATE = 0x03 – Link up

Thanks and regards,

Hideaki

over 1 year ago

0 Pekka Varis over 1 year ago

TI__Mastermind 27050 points

There is a significantly updated PCIe driver and associated users guide. Unfortunately this did not make the MCU+ 9.2. We can deliver a version over TI drive if that is ok?

Pekka

0 Hideaki Matsumoto over 1 year ago in reply to Pekka Varis

TI__Genius 9640 points

Hi Pekka,

Thank you for your response. Yes, please share it over TI drive.

Thanks and regards,
Hideaki

0 Pekka Varis over 1 year ago in reply to Hideaki Matsumoto

TI__Mastermind 27050 points

Sorry, on second look it looks like probably not something where the new version would make a difference. First suspect here is the cable and the modifications.

Pekka

0 Dominic Rath over 1 year ago in reply to Pekka Varis

Mastermind 7620 points

Hello Hideaki,

Hideaki Matsumoto said:
PCIe cable should be something special ?

From the documentation on the 3M site it looks like this cable is 1:1, but they need a cable that connects RX->TX and TX-> RX. I believe that's what you meant when you say "is modified to connect A16/A17 of RC on EVM #1 to B14/B15", but it's not clear from that brief description.

TI recommends a different cable in the MCU+ documentation: See the description e.g. here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/09_02_00_50/exports/docs/api_guide_am64x/EXAMPLES_DRIVERS_PCIE_BENCHMARK_RC.html

I can confirm that with this cable the examples in MCU+ SDK work out of the box.

Hideaki Matsumoto said:
RC (Other SoC Board) <---- (PCIe supported Cable) ----> EP (TMDS64EVM #2)

Is that "PCIe supported Cable" the same cable they used when testing EVM<->EVM? Their interpretation of the link status register is correct. In that "other SOM <-> AM64x" case the link was up.

Some other things to consider:

what revision is their EVM? There have been modifications how the PCIe reference clock is generated (early revision connected directly to AM64x, later revisions have a clock generator that feeds both the connector and the AM64x)
due the first point the RefClk pins should /not/ be connected, because otherwise the RefClk generator on both EVM's are driving the same lines
the EVM schematics include notes on J35 and J34 jumper settings for RC vs. EP, but I doubt that causes an issue in this case

Regards,

Dominic

Processors

Processors forum

AM6442: PCIe cannot link-up