Can it be possible to interface a standard 1GB JEDEC 200pins SO-DIMM to TI TMS320DM8168 or DM8147 ?
These modules have 64 bits data bus. While TI has 2 x 32 bits data bus.
I noticed that the datasheet on the memory controller refer to various modes:
- 1 DDR channel EMIF0 without interlacing
and
- 2 DDR channels EMIF0 & EMIF1 with or withtout interleaving (boot.selectable)
Maybe the 64bits bus width can be supported in interleaved mode as long as I
only use the address bus of EMIF0 to be sent to all the SO-DIMM chips, while
interfacing the EMIF0 to bits [0..31] of SO-DIMM and the EMIF1 to bits [32.63] of SO-DIMM.
And leaving the address bus of EMIF1 open or connected to dummy loads.
Here is an extract fronm the DM814x about memory controller that refers to a TBD document:
Refer to TMS320DM814x DMSoC LPDDR/DDR2/DDR3 Memory Controller User's Guide (TBD)
I may get the answer in this TBD inexistant document ?
Maybe there a similar document for a previous TI chip that also use memory manager with interleaved channels EMIF0 and EMIF1
where I can get my answer ?
Also is there a performance hit if I want to do 1080p @60Hz video acquisition and h.264 compression
when the DDR memory controller interleaved mode is disabled ? SInce memory controller would
have to generate incremental adresses rather than inerleaved adresses.
Full section in datasheet of DM8147
MEMORY CONTROLLER
--------------------------------
LPDDR/DDR2/DDR3 Memory Controller
The device has a dedicated interface to DDR3, DDR2, and LPDDR SDRAM. It supports JEDEC standard
compliant LPDDR, DDR2 and DDR3 SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, and 2Gb devices
• Support for two independent chip selects, with their corresponding register sets, and independent page
tracking
• Two interfaces with associated LPDDR/DDR2/DDR3 PHYs
• Dynamic memory manager allows for interleaving of data between the two DDR interfaces.
For details on the LPDDR/DDR2/DDR3 Memory Controller, see the TMS320DM814x DMSoC
LPDDR/DDR2/DDR3 Memory Controller User's Guide (TBD).
Gilbert
Muxlab.com
