AM623: M4F timers - Counter Compare

Hi Rafael, could you explain me how you are planning to use "Counter Compare"?. As you mentioned, I don't see either a specific API for counting in our KERNEL DPL CLOCK module. So, you would probably need to use EPWM for Counter/Compare.

From MCU-SDK example (I checked epwm_duty_cycle_am62x-sk-lp_m4fss0-0_freertos_ti-arm-clang) it seems to me we start/stop EPWM by enabling/disabling Event-trigger submodule.

Links to online AM62x MCU SDK User Guide:

AM62x MCU+ SDK: EPWM Duty Cycle (ti.com)

AM62x MCU+ SDK: EPWM (ti.com)

Thank you,

Paula

Hello!

Basically, I need to make a pulse train output, where I will receive information on how many pulses I should generate at each frequency and, after finishing the determined number of pulses, I change the frequency and generate another number of pulses, all with a constant duty cycle of 50%. All this with the same signal. As exemplified in the diagram below:

EPWM modules are already being used to make PWM outputs, and I believe we will not be able to change that. The intention was to be able to formulate this algorithm based on the output compare feature, where the timer count would increase and, when it reached a certain level, before the overflow, it would generate an event, thus simulating the rising and falling edges and forming a signal during a complete timer counting cycle, ending in its overflow. I don't know if it was necessarily clear.

Looking at the EPWM libraries, I noticed that they work this way too, with comparison values. I asked myself if I wouldn't be able to do this with a feature like this within the M4F timers, or if I would have to resort to alternative ways. If not, do you have any suggestions on what direction to take?

Thank you very much,
Rafael Volkmer

Hi Rafael, please allow me some time to check this. I will come back to you next week

thank you,

Paula

My specification for this specific output would be:

Hi Rafael, I am trying to see internally with some colleagues if there is any other option

thank you,

Paula

Hello! Another thing, about this example here: AM62x MCU+ SDK: EPWM Duty Cycle (ti.com)

Was it supposed to, after the 60s passed, the EPWM signal turn off?

Correct, from AM62x MCU+ SDK User Guide we have:

EPWM Duty Cycle

• Configures ePWM0 to generate a 1KHz signal with 25% duty cycle for 60 seconds.

AM62x MCU+ SDK: EPWM Duty Cycle (ti.com) 

thanks,

Paula

In my tests running this example, I had a pwm that never stopped running. I've made some small changes, including moving to a bare metal environment and not RTOS and, here the comparison of the two signals on pin 24 of the devkit am623 io expander (encapsulally ALW).

The two tests recorded and compared:

www.youtube.com/watch

But what about the timers here? I saw this diagram and descriptions of features in the AM623 reference manual and found this information, however, without abstractions for them. Is there any example or something similar related to this?

Hi Rafael, let us check and come back to you

thanks

Paula

Hi Rafael, 

Yes, it is possible with Timer PWM as well. But, in our MCU+SDK, we use it for timer purposes.

But, for your requirement generate the PWM signal frequency with a 50% duty cycle is possible and remaining functionality, like controlling no of pulses and frequency changes and driving pwm low or high based on your requirement should be controlled by you.

I can try to provide steps for how to do itSo, that you can try at your side and let us know the status .

Regards,

Anil.

Can i just throw this files at empty project example on MCU+SDK and configure the sysconfig file here, right?

"this files" i mean main.c and hello_world.c

Hello Rafael,

Yes, you are correct. I have created an example on the hello_World project., you need to copy main. C and hell_world.c file functions in to  your project.

I have not configured any system config since don't support this feature from system cfg and everything I have done manually .

Regards,

Anil.

Can you please tell me what calculation was set to adjust the frequency to 5khz and the duty to 50%? I am adjusting the frequencies and getting a gap in what I want

I'm trying to adapt the function to pass the frequency and duty cycle to the PWM signal, however, without success, due to the nature of the calculation. Do you have any ideas? And, also, there is a maximum frequency for the PWM signal, because I need to reach 200khz.

im trying something like that

Hello Rafael,

I am not sure which duty you are trying ? Is not 50% duty ?

I have added my comments above that this example can work for 50% duty if you need other than 50% duty. In the same example, you need to enable TMAR configurations as well. But, in your experiment you said that you need only 50% duty .

For 200Khz signal, what is the macro value you are passing ?

Regards,

Anil.

for the PTO, 50% duty cycle is fine, however, I also need to develop a PWM interface with the same peripherals. The need to change the duty cycle in a scale of 1% - 99% is there. In this case, for 200khz I used this, and works nice:

Now, the frequency is a problem

When i get this, generate a 4khz wave: 

Hello Rafael,

Please look at the image below.

The PWM is generated based on either overflow or overflow and match type.

Currently, I have enabled with overflow.

So, frequency and duty values are purely based on overflow value.

For example, if you need a 10% duty cycle with 1 KHz frequency.

TON = 10% * 1K and TOFF = 90% * 1K. So, in this time period you need to change  for every time in the Timer ISR routine .

If you need to 200KHz with different duties from 1% to 99%.

We are feeding a 25MHz clock to the time without any scaling.

For 1% duty, TON = 1% of 200KHZ and the remaining TOFF = 99% of 200KHz time should be loaded.

So, for every time you need to load the TON and TOFF periods in the ISR routine, this way you can achieve different duties and frequencies.

There is a TIMER_MAR register to see if this register can be used for duty and the over overflow timer can be used for frequency and try with this method also.

Regards,

Anil.

Hello!

Currently, my code is like this. I studied a little about how TMAR works:

#define USR_TIMER_IRQ_EOI           (0x20u)
#define USR_TIMER_IRQ_STATUS_RAW    (0x24u)
#define USR_TIMER_IRQ_STATUS        (0x28u)
#define USR_TIMER_IRQ_INT_ENABLE    (0x2Cu)
#define USR_TIMER_IRQ_INT_DISABLE   (0x30u)
#define USR_TIMER_TCLR              (0x38u)
#define USR_TIMER_TCRR              (0x3cu)
#define USR_TIMER_TLDR              (0x40u)
#define USR_TIMER_TMAR              (0x44u)
#define USR_TIMER_OVF_INT_SHIFT     (0x1)

void PWM_timSetup(uint32_t baseAddr, uint32_t frequency, uint32_t duty)
{
    volatile uint32_t *addr;
    uint32_t ctrlVal;
    uint32_t timerCycles;
    uint32_t countVal;
    uint64_t tmarValue;

    TimerP_stop(baseAddr);
    TimerP_clearOverflowInt(baseAddr);

    timerCycles = 25000000U / frequency ;

    countVal = 0xFFFFFFFFU - timerCycles + 1U;

    tmarValue = countVal + ( timerCycles * (duty/ 100U) );

    ctrlVal = 0;

    addr = (volatile uint32_t *)(baseAddr + USR_TIMER_TCLR);
    CSL_REG32_WR(addr, ctrlVal);

    ctrlVal = (1 << 10U) | (1 << 12U) | (1 << 1);
    CSL_REG32_WR(addr, ctrlVal);

    addr = (volatile uint32_t *)(baseAddr + USR_TIMER_TLDR);
    CSL_REG32_WR(addr, countVal);

    addr = (volatile uint32_t *)(baseAddr + USR_TIMER_TMAR);
    CSL_REG32_WR(addr, tmarValue);
}

However, still without success. I don't know if I misinterpreted something in the documentation.

Hello Rafael,

Can you please try the code below and I have verified at 200KHz with 1% duty and 99% and all working as expected.

You need to check for all frequencies and duties and I have not verified for all frequencies.

You need to pass two parameters, one for frequency and duty.

For frequency, you need to pass time in nsec.

For example, you need a 200KHz frequency and the time period is 5usec and this value needs to convert to nsec values.

So, you need to pass 

 #define TIMER_PERIOD (5000) //in Nsec

and duty values from 0 to 100%

If duty is 50% duty, then go ahead with the overflow method. 

If duty is other than 50%, then you go ahead with overflow and match mode.

For 0% duty, either you can set no trigger method or set the SCPWM bit  as low. 

For 100% duty, you can set a pin as high with the help of SCPWM bit as high. 

I have seen one observation while continuously  writing TCLR register is not allowing to update new writes operation .

We need to check whether this operation is completed  or not before proceeding  for new change in TCLR register .

I am assume that this might be problem with Core Clock and Timer interface clock will be different .I can confirm .

4101.hello_world_am64x-evm_m4fss0-0_nortos_ti-arm-clang.zip

Regards,

Anil.

If i just start the code by code composer, it provides me a 50% duty 1khz. But, if i build step by step, the duty is working but the frequency is 3khz. I just change my timer for MCU_TIMER3 and TIMER_IO3. Any idea where is the problem?

With the values 45 for duty and 5000 for period, i got this (Just debugging step by step):

Without being step by step, I only achieve this in 100% of situations:

Hello Rafael,

Please look at the image below and I got frequency 200KHz and duty is 44%.

I am not sure why you are having strange behavior.

Did you integrate my changes into your application ?

How are you loading an application from CCS or Linux ?

Can you do POR or warmest the devices and load the application and still see if you have an issue ?

How did you feed duty and frequency values in application ? You are changing them frequently  in the code or only calling for one time.

Regards,

Anil.

Hello! The only modification i made is the timer instance:

The code is the same that you give to me.

Im loading my aplication by CCS.

Still my code run properly only step by step debug on CCS.

Hello Rafael,

The first problem is that your application is not properly selecting the correct clock for Timer 3.

For the Timer 3 clock selection we need to use the address below.

So, you need to change the red-colored with to the 0x450806C address.

Rafael Volkmer said:

Still my code run properly only step by step debug on CCS.

Yes, I have also seen the same issues. We need to enable synchronization between Core and Timer modules while writing in to Timer Registers .

I have seen some registers are there to synchronize between writing operations of each Timer Register.

So, we need to check for each write writing operation whether the writing operation is done or not .

Now, you can go ahead with the single step execution from CCS to update values in to TCLR registers .

Now, you can see whether you are able to get the proper frequency and duty values with the above code .

Later, we will work on how to solve this issue .

Regards,

Anil.

I made some modifications, but nothing that changed the logic. I'm still stuck on a duty_cycle that works and a frequency of 3hz to 5000. I tested it on my home setup at night and I managed to reach 200khz, however, on the company setup, only 3hz. I don't know exactly what's wrong.

#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"

/* ----------- TimerP ----------- */
#include <kernel/dpl/TimerP.h>


void TimerP_isr0(void *args);
void pwm_Timer_setup(uint32_t baseAddr);


extern uint32_t gTimerBaseAddr;

volatile uint32_t  noofsamples = 0U;

#define USR_TIMER_IRQ_EOI           (0x20u)
#define USR_TIMER_IRQ_STATUS_RAW    (0x24u)
#define USR_TIMER_IRQ_STATUS        (0x28u)
#define USR_TIMER_IRQ_INT_ENABLE    (0x2Cu)
#define USR_TIMER_IRQ_INT_DISABLE   (0x30u)
#define USR_TIMER_TCLR              (0x38u)
#define USR_TIMER_TCRR              (0x3cu)
#define USR_TIMER_TLDR              (0x40u)
#define USR_TIMER_TMAR              (0x4Cu)

#define USR_TIMER_OVF_INT_SHIFT     (0x1)

#define USR_TIMER_MATCH_INT_SHIFT     (0x0)


#define PWM_TCLR_SCPWM_BIT_MSK     (0x7U)


#define TIMER_PERIOD (5000) //in Nsec

#define TIMER_INPUT_CLOCK     (25000000UL)

#define PWM_DUTY_0_PERCENT   0U

#define PWM_DUTY_100_PERCENT 100U

#define PWM_DUTY_50_PERCENT  50U

#define USR_PWM_DUTY_PERCENT_CONFIG  90U


void Pwm_SetPeriodAndDuty(uint64_t Period, uint8_t DutyCycle);


volatile uint8_t Test_Variable = 0U;

volatile uint64_t Test_Frequency = 0U;
volatile uint8_t Test_Duty = 0U;

void hello_world_main(void *args)
{
    /* Open drivers to open the UART driver for console */
    Drivers_open();
    Board_driversOpen();
    Pwm_SetPeriodAndDuty(TIMER_PERIOD,USR_PWM_DUTY_PERCENT_CONFIG);

    TimerP_start( gTimerBaseAddr );

    while(1)
    {
//        switch(Test_Variable)
//        {
//          case 0U:
//              Pwm_SetPeriodAndDuty(TIMER_PERIOD,PWM_DUTY_0_PERCENT);
//          break;
//          case 1U:
//              Pwm_SetPeriodAndDuty(TIMER_PERIOD,PWM_DUTY_50_PERCENT);
//          break;
//          case 2U:
//              Pwm_SetPeriodAndDuty(TIMER_PERIOD,PWM_DUTY_100_PERCENT);
//          break;
//          case 3U:
//              Pwm_SetPeriodAndDuty(Test_Frequency,PWM_DUTY_50_PERCENT);
//          break;
//          case 4U:
//              Pwm_SetPeriodAndDuty(Test_Frequency,Test_Duty);
//          break;
//          default :
//              Pwm_SetPeriodAndDuty(TIMER_PERIOD,PWM_DUTY_0_PERCENT);
//           break;
//        }
    }
    DebugP_log("Hello World!\r\n");

    Board_driversClose();
    Drivers_close();
}

void pwm_Timer_setup(uint32_t baseAddr)
{
    volatile uint32_t *addr;
    volatile uint32_t ctrlVal = 0x00;
    volatile uint32_t countVal, reloadVal;
    volatile uint64_t timeInNsec, inputClkHz, timerCycles;

    volatile uint8_t enableOverflowInt = FALSE;

    /* stop timer and clear pending interrupts */
    TimerP_stop(baseAddr);
    TimerP_clearOverflowInt(baseAddr);

    timeInNsec = (uint64_t)TIMER_PERIOD / 2U;

    inputClkHz = 25000000U / 1U;
    timerCycles =  ( inputClkHz * timeInNsec ) / 1000000000U;

    /* if timerCycles > 32b then we cannot give accurate timing */
    DebugP_assert( timerCycles < 0xFFFFFFFFU );

    /* calculate count and reload value register value */
    countVal = 0xFFFFFFFFU - (timerCycles - 1U);

    /* keep reload value as 0, later if is auto-reload is enabled, it will be set a value > 0 */
    reloadVal = countVal;

    /* calculate control register value, keep timer disabled */
    ctrlVal = 0;

    /* set timer control value */
    addr = (volatile uint32_t *)(baseAddr + USR_TIMER_TCLR);
    CSL_REG32_WR(addr,ctrlVal);


    ctrlVal =  ( (1<<10U) | (1<<12U) | (1<<1) ); //Trigger on overflow, Toggle, enable Auto Reload Mode
    CSL_REG32_WR(addr,ctrlVal);


    /* set reload value */
    addr = (volatile uint32_t *)(baseAddr + USR_TIMER_TLDR);
    CSL_REG32_WR(addr,reloadVal);


    /* set timer count value */
    addr = (volatile uint32_t *)(baseAddr + USR_TIMER_TCRR);
    CSL_REG32_WR(addr,countVal);

    /* enable/disable interrupts */
    if(enableOverflowInt == TRUE)
    {
        /* enable interrupt */
        addr = (volatile uint32_t *)(baseAddr + USR_TIMER_IRQ_INT_ENABLE);
        ctrlVal = (0x1U << USR_TIMER_OVF_INT_SHIFT)| (0x1U << USR_TIMER_MATCH_INT_SHIFT);
        CSL_REG32_WR(addr,ctrlVal);

    }
    else
    {
        /* disable interrupt */
        addr = (volatile uint32_t *)(baseAddr + USR_TIMER_IRQ_INT_DISABLE);
        ctrlVal = (0x1U << USR_TIMER_OVF_INT_SHIFT) |  (0x1U << USR_TIMER_MATCH_INT_SHIFT);
        CSL_REG32_WR(addr,ctrlVal);

    }

}

void Pwm_SetPeriodAndDuty(volatile uint64_t Period_count, volatile uint8_t DutyCycle)
{

    volatile uint32_t regVal;
    volatile uint64_t Period;
    volatile uint32_t absolute_dutyCycle;
    volatile uint32_t TLDR_VALUE             =        0U;
    volatile uint32_t TMAR_VALUE             =        0U;

    /* Handle boundary conditions of 0% */
    /* Handle boundary conditions of 100% */
    if (PWM_DUTY_0_PERCENT == DutyCycle)
    {
        /* For 0% Dutycycle Output is inverse of configured polarity parameter
         * disable timer */
        TimerP_stop( gTimerBaseAddr );


        regVal = CSL_REG32_RD(gTimerBaseAddr + USR_TIMER_TCLR);
        regVal &= (~((uint32_t)1U<< PWM_TCLR_SCPWM_BIT_MSK));
        CSL_REG32_WR((gTimerBaseAddr + USR_TIMER_TCLR), regVal);
    }
    else if (PWM_DUTY_100_PERCENT == DutyCycle)
    {
        /* For 100% Dutycycle Output is equal configured polarity parameter
         * disable timer */
        TimerP_stop( gTimerBaseAddr );

        regVal = CSL_REG32_RD(gTimerBaseAddr + USR_TIMER_TCLR);
        regVal |= ((uint32_t)1U<< PWM_TCLR_SCPWM_BIT_MSK);
        CSL_REG32_WR((gTimerBaseAddr + USR_TIMER_TCLR), regVal);
    }
    else
    {

        regVal = CSL_REG32_RD(gTimerBaseAddr + USR_TIMER_TCLR);
        regVal &= ~((uint32_t)1U<< PWM_TCLR_SCPWM_BIT_MSK);
        CSL_REG32_WR( (gTimerBaseAddr + USR_TIMER_TCLR) , regVal);

        Period =  (  ( TIMER_INPUT_CLOCK * Period_count ) / 1000000000U );

        /* Calculating absolute duty cycle in ticks */
        absolute_dutyCycle = Period - ( (Period * DutyCycle )/ 100U );
        /* Calculating Reload and Compare register values  */
        if (PWM_DUTY_50_PERCENT == DutyCycle)
        {
            /* set timer control value */
            regVal = CSL_REG32_RD(gTimerBaseAddr + USR_TIMER_TCLR);
            regVal &= ~( (1<<11U) | (1<<6U)  );
            regVal |= ( (1<<10U) );
            CSL_REG32_WR( (gTimerBaseAddr + USR_TIMER_TCLR),regVal);

            TLDR_VALUE = (Period) / 2U;

            /* set timer Match value */
            CSL_REG32_WR( (gTimerBaseAddr + USR_TIMER_TMAR),0U);
        }
        else
        {
            /* set timer control value */
            regVal = CSL_REG32_RD(gTimerBaseAddr + USR_TIMER_TCLR);
            regVal &= ( ~ (1<<10U) );
            regVal |= ( (1<<11U) | (1<<6U) );

            TLDR_VALUE = (Period);

            TMAR_VALUE = 0xFFFFFFFFU - absolute_dutyCycle - 1U;

            /* set timer count value */
            CSL_REG32_WR((gTimerBaseAddr + USR_TIMER_TMAR),TMAR_VALUE);
            CSL_REG32_WR((gTimerBaseAddr + USR_TIMER_TCLR),regVal);

        }

        TLDR_VALUE = 0xFFFFFFFFU - (TLDR_VALUE - 1U);

        /* set timer count value */
        CSL_REG32_WR((gTimerBaseAddr + USR_TIMER_TCRR),TLDR_VALUE);

        /* set reload value */
        CSL_REG32_WR((gTimerBaseAddr + USR_TIMER_TLDR),TLDR_VALUE);

        return;
    }
}

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 *  modification, are permitted provided that the following conditions
 *  are met:
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 *    notice, this list of conditions and the following disclaimer.
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdlib.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include <kernel/dpl/HwiP.h>
#include <kernel/dpl/TimerP.h>
#include <drivers/pinmux.h>

void hello_world_main(void *args);
void Timer_Pin_config(void);

uint32_t gTimerBaseAddr = 0U;

extern void pwm_Timer_setup(uint32_t baseAddr);

int main(void)
{
    System_init();
    Board_init();
    Timer_Pin_config();

    hello_world_main(NULL);

    Board_deinit();
    System_deinit();

    return 0;
}

void Timer_Pin_config(void)
{
    TimerP_Params timerParams;

    /* set timer clock source */
    SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MCU, 0);
    *(volatile uint32_t*)AddrTranslateP_getLocalAddr(0x4508068U) = 0x0;
    SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MCU, 0);

    gTimerBaseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CSL_MCU_TIMER3_CFG_BASE);

    TimerP_Params_init(&timerParams);
    timerParams.inputPreScaler = 1U;
    timerParams.inputClkHz     = 25000000U;
    timerParams.periodInNsec   = 0U;
    timerParams.oneshotMode    = 0U;
    timerParams.enableOverflowInt = 0U;
    timerParams.enableDmaTrigger  = 0U;
    TimerP_setup(gTimerBaseAddr, &timerParams);

    pwm_Timer_setup(gTimerBaseAddr);

    Pinmux_PerCfg_t Timer_pin_Cfg[] =
    {
       {
           PIN_MCU_MCAN1_RX,
           ( PIN_MODE(1)  | PIN_PULL_DISABLE )
       },

            {PINMUX_END, PINMUX_END}
    };


    Pinmux_config(Timer_pin_Cfg, PINMUX_DOMAIN_ID_MCU);
}

Rafael Volkmer said:

I made some modifications, but nothing that changed the logic. I'm still stuck on a duty_cycle that works and a frequency of 3hz to 5000. I tested it on my home setup at night and I managed to reach 200khz, however, on the company setup, only 3hz. I don't know exactly what's wrong

Hello Rafel,

If the timer clock selection is other than 25MHz, then the PWM frequency will be different according to the 5000 Counter value for 200KHz.

So, please confirm did you change the clock selection address in both your setups or not ?

Swargam Anil said:

For the Timer 3 clock selection we need to use the address below.

So, you need to change the red-colored with to the 0x450806C address.

Even if you change the clock selection address and does not come proper PWM signal frequency, then check the TMAR and TLDR registers are properly loaded with your input or not.

I have verified that I am able to get 200KHz from 1% to 99% duty and only issue with the TCLR registers need some more time to update it s values .

Regards,

Anil.