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TDA4VL-Q1: Differences between PMIC WDG Configuration Rev3 and Rev5 [TPS6594133A ]

Hind Ashraf
Intellectual 900 points
Part Number: TDA4VL-Q1

Tool/software:

-Now we have a new sample of PMIC REV5 ,there's an observation on behavior that ECU reset .


-What need to be clarified :

  1.  what does rev5 stands to?
  2. what're differences between Rev3 and Rev5 ?
  3. Is there any needed configuration shall be updated to adapt the Rev5 didn't handled in Rev3?
  • 0
    TI__Mastermind 25805 points

    Hello Hind,

    Hind Ashraf said:
    -Now we have a new sample of PMIC REV5 ,there's an observation on behavior that ECU reset .

    What is the observation you are seeing?

    Changes from Rev 3 to Rev 5 on TPS6594133A

    • The TO_ACTIVE sequence changed to include 500us delay between LDO3 and BUCK5. This was part of new sequence timing requirement from the TDA4 team. This allows PMIC BUCK5 to power up fully before LDO3. Overall sequence time remains the same. 
    • Watchdog enabled by default with 13 min Long Window. This is to correctly reflect the documentation of the TPS6594133A. MCU SW must boot and configure watchdog within 13 minutes of nRSTOUT going high or disable via I2C
    • GPIO9 boots as an input to set the WD_PWRHOLD, then changes to an output to enable the external 3.3V load switch in the PDN. This give customer the option to use an external pull up resistor to set WD_PWRHOLD=1.
    • LDO2 OV/UV default threshold changed from 5% to 10%. Customer can tighten after boot.