DM8168 - DDR3 Interleaving Doesn't work

Hello,

Can you please provide more details on what you mean by "my design doesn't work straight with interleaving"?

Regards,
Marc

Hi,

My Design means a custom hardware with Netra processor and 4 x DDR3 (4 x 2Gb= 1GB).

DDR0 and DDR1 controller each has 2x16 2Gb DDR3 (512MB). On this custom design individually 512MB DDR3 on DDR0 and DDR1 are working fine but interleaving similar to EVM doesn't work.

I am not sure if it needs some register change.

Thanks,

Mihir Shah

Mihir,

Did you verify the correct settings in register DMM_LISA_MAP_0-DMM_LISA_MAP_3?

Regards,
Marc

Mihir,

Here are a couple of other questions/comments:

1. Can you please clarify what you mean by "interleaving similar to EVM doesn't work"? Does EMIF access always fail or does it fail at certain address ranges?
2. The DMM requires that when interleaving is enabled the electrical characteristics of both EMIF interfaces need to be similar.  You may need to check the routing of both EMIFs.

Regards,
Marc

Hi Marc,

1) With interleaving enabled, I am able to access every alternate 32words successfully. 32words alternately are not accessible.

2) Electrical characteristic of both EMIF mean? Do we need length matching of EMIF1 and EMIF2?

We tried following values for interleaving,

DMM_LISA_MAP__0 - 0x80640300 and 0x80540300
DMM_LISA_MAP__1 - 0xC0640320 and 0xC0540320
DMM_LISA_MAP__2 - 0x80640300 and 0x80540300
DMM_LISA_MAP__3 - 0xC0640320 and 0xC0540320

Currently we have disabled interleaving temporary and checked both DDR0 and DDR1 working, both works fine.

DMM_LISA_MAP__0 - 0x80500300
DMM_LISA_MAP__1 - 0xC0500320
DMM_LISA_MAP__2 - 0x80500300
DMM_LISA_MAP__3 - 0xC0500320

Regards,

Mihir

Hi Marc,

Following are the length matching rules

Hi Marc,

Let me add to Mihir's point about  "1) With interleaving enabled, I am able to access every alternate 32words successfully. 32words alternately are not accessible." in earlier post.

- We have set SDRC_INTL = 1h (128 byte interleaving). With this, if we access any address let's say 0x80000000. Then We are able to access 128 bytes perfectly fine (which comes from DDR0 controller), next 128 bytes are read as always 0 in CCS memory window and not accessible for write (which comes from DDR1 controller), again 128 bytes are perfectly fine for read/write operation and this continues for whole 1 GB.

Let me share one more important observation for DDR1 controller.

In GEL file/UBoot code, following patchwork is done for both DDR controllers' SDRAM_REF_CTRL registers.

Step1: EMIF4_1_SDRAM_REF_CTRL = 0x0000613B //Initially a large refresh period

Step2: EMIF4_1_SDRAM_REF_CTRL = 0x1000613B //Trigger initialization

Step3: EMIF4_1_SDRAM_REF_CTRL = 0x10000000|SDREF //Move to a smaller more correct one

Step 3 is not working for DDR controller 1 but it works for DDR controller 0. The processor hangs when above step is performed for DDR controller 1.

Queries

1) Can this be root cause of interleaving issue ?

2) S/w leveling is done as per the values (derived by CCS program) calculated for trace length of DDR 0 controller. Can this be issue for interleaving ?

Thanks,

Sweta

Mihir,

It looks like the content of some of your posts was deleted some how.  Could you please repost your updates on this issue?

Thanks,
Marc

Marc,

I am sorry for confusion, but nothing got deleted. Those are blank posts by mistake.