In the System Interconnect Diagram of the L138 showing all of its switched central resources and bridges there is shown three ARM bridges connected to one ARM SCR: BR1 BR2 and BR0 connected to SCR0. How are the bridges selected by ARM-mastered transactions? e.g. Do all accesses to mDDR go through BR1? Do all accesses to EMIFA go out BR0? Are there particular ARM instructions that result in BRX selection?
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
