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C667x SRIO - what memory regions does external device have access to?

pathfinder
Genius 12790 points


When external device accesses C667x memory, external or internal, what does it have access to?  First pass through of data sheet and SRIO UG, found info that says SRIO will talk to L2 memory.  Is this the only SRC/DST for SRIO xactions?

 

Thanks.

  • 0
    TI__Guru* 84110 points

    Marc,

    At some point, we will have an interconnect diagram in the C6678 (assuming that is the C667x device you are using) datasheet to help show how the various bus masters like SRIO are connected to the rest of the device. For now, Table 4-1 "Switch Fabric Connection Matrix" details which slave ports within the device can be driven by which bus masters.

    You can see in the table that the SRIO Packet DMA and SRIO Master are connected to all of the CorePac SDMA ports (for access to L1 and L2 memories) and the MSMC SMS (SRAM) and SES (DDR3) slave ports.

    Any other specifics that you want to know about which addresses can be driven by the SRIO masters are also in that table.

    Remember to use the Global L1 and L2 addresses when accessing the CorePac internal memories.

    Regards,
    RandyP

     

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