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TDA4VH-Q1: TDA4VH DDR Reset waveform

jingle.lan
Prodigy 80 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi all：

  In the TDA4VH power-on timing test, we found that the Reset pin waveform of DDR was as follows, with 20mv fluctuation. This voltage was within the high level threshold of the Reset pin of DDR, and the jitter disappeared after the Cold Reset of TDA4VH turned to high level.We tested at TP702 point, and this was true for all four DDR waveforms.DDR model: MT53E2G32D4DE-046 AAT:CD

  Please help to confirm the cause of this problem. I think this change has no impact on the start-up of TDA4 before the Cold Reset, but we need TI's confirmation.

     

  • 0
    TI__Mastermind 28445 points

    Hi,

    jingle.lan said:
    and the jitter disappeared after the Cold Reset of TDA4VH turned to high level.

    The TDA4VH device is in reset while this measurement is being taken?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 80 points

    Hi Kevin ，This waveform is the TDA4 power-on process, the cold reset is controlled by MCU-TC397, and the cold reset  level is low at this time.

  • 0 in reply to jingle.lan
    TI__Mastermind 28445 points

    Hi,

    If PORz and MCU_PORz are low, this means that the TDA4VH device is in reset. 

    The RESET_n of the LPDDR4 memory should be driven low (to reset the memory) as part of the DDRSS and LPDDR4 initialization sequence after the TDA4 is taken out of reset. The schematic image you provided shows that RESET_n has a weak pull down resistor which should keep the signal low prior to being driven low by the TDA4 device. Thus, I am not really clear why you observe RESET_n high. Maybe check whether R701 was populated on the PCB instead of R702? 

    Typically, RESET_n should be low while voltages of the LPDDR4 are ramped. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 80 points

    Hi Kevin，

        We provided the wrong information before, Porz and MCU_Porz are both high at this time, and TDA4 should be starting, but the Reset waveform of DDR is green in the figure, and it does have some fluctuations, but within the high level range, please confirm. There is no patch on the pull-up resistor. This signal is output by TDA4VH, we can confirm it.

    Thanks

  • +1 in reply to jingle.lan
    TI__Mastermind 28445 points

    Hi,

    Ok, thanks for the additional information and clarification. As you mentioned, the voltage level should still be well above the LPDDR4 VIH requirement for RESET_n, so this should not be an issue.

    Regards,
    Kevin