Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello all,
I am having trouble reading register values from the MCP23S17 SPI expander we are using with our AM6421B processor. To start with, we are using the MCSPI TI driver to address our SPI devices, including the MCP23S17. The main function for doing this comes from the iolink_master_demo in the industrial comms SDK version 9.2.0.8 named iolm_port_spi.c. This is the function:
int32_t IOLM_SPI_mcspiTransfer( uint32_t mcspiInstance, uint32_t mcspiChannel, uint32_t mcspiDataSize, uint8_t *pTxData, uint8_t *pRxData, uint32_t lengthInBytes) { uint32_t lengthInBits; uint32_t lengthInWords; int32_t error; MCSPI_Transaction *pTransaction; // check the platform MCSPI_Transaction transaction; pTransaction = &transaction; if ((mcspiInstance >= CONFIG_MCSPI_NUM_INSTANCES) || (mcspiChannel >= MCSPI_MAX_NUM_CHANNELS) || (gMcspiConfig[mcspiInstance].object == NULL)) { error = SystemP_FAILURE; OSAL_error( __FILE__, __LINE__, OSAL_eERR_INVALIDSTATE, true, 1, "SPI setup does not match sysCfg SPI setup or SPI init failed.\r\n"); goto laExit; } /* convert length in bytes to frames with channel/instance configuration specific width */ lengthInBits = lengthInBytes * 8; lengthInWords = lengthInBits / mcspiDataSize; if ((lengthInBits % mcspiDataSize) > 0) { lengthInWords++; } MCSPI_Transaction_init(pTransaction); // load data to the cache if (MCSPI_OPER_MODE_DMA == ((MCSPI_Config *)gMcspiConfig[mcspiInstance].object->handle)->attrs->operMode) { CacheP_wb(pTxData, lengthInBytes, CacheP_TYPE_ALLD); CacheP_wbInv(pRxData, lengthInBytes, CacheP_TYPE_ALLD); } pTransaction->channel = mcspiChannel; pTransaction->txBuf = pTxData; pTransaction->rxBuf = pRxData; pTransaction->dataSize = mcspiDataSize; pTransaction->count = lengthInWords; pTransaction->csDisable = TRUE; error = MCSPI_transfer(gMcspiConfig[mcspiInstance].object->handle, pTransaction); laExit: return error; }
// Write to IOCON.HAEN // A2 is set here in the address - not sure if this is correct. 0A is // the register address of IOCON when IOCON.BANK = 0. uint16_t txBuf[2] = {0x480Au, 0u}; // Intended to set bit 3 in IOCON. uint8_t u8txBuf = 0x08u; int32_t error = SystemP_SUCCESS; error = IOLM_SPI_mcspiTransfer(CONFIG_MCSPI_SPI1, MCSPI_CHANNEL_0, 16u, txBuf, NULL, 4u); DebugP_assert(error == SystemP_SUCCESS); error = IOLM_SPI_mcspiTransfer(CONFIG_MCSPI_SPI1, MCSPI_CHANNEL_0, 8u, &utx8Buf, NULL, 1u); DebugP_assert(error == SystemP_SUCCESS);
// 0x49 = address pin A2 set, and read // 0x12 = address of GPIOA register when IOCON.BANK = 0. uint16_t txBuf = 0x4912; uint16_t rxBuf = 0u; int32_t error = SystemP_SUCCESS; error = IOLM_SPI_mcspiTransfer(CONFIG_MCSPI_SPI1, MCSPI_CHANNEL_0, 16u, &txBuf, &rxBuf, 3u); DebugP_assert(error == SystemP_SUCCESS);
mcspi1.intrEnable = "POLLED"; mcspi1.mode = "MULTI_CONTROLLER"; mcspi1.$name = "CONFIG_MCSPI_SPI1"; mcspi1.advanced = true; mcspi1.SPI.$assign = "SPI1"; mcspi1.SPI.CLK.$assign = "SPI1_CLK"; mcspi1.SPI.D0.rx = false; mcspi1.SPI.D0.$assign = "SPI1_D0"; mcspi1.SPI.D1.$assign = "SPI1_D1"; mcspi1.child.$name = "drivers_mcspi_v0_mcspi_v0_template0"; mcspi1.mcspiChannel.create(2); mcspi1.mcspiChannel[0].$name = "CONFIG_MCSPI_SPI1_CS0"; mcspi1.mcspiChannel[0].advanced = true; mcspi1.mcspiChannel[0].CSn.rx = false; mcspi1.mcspiChannel[0].CSn.$assign = "SPI1_CS0"; mcspi1.mcspiChannel[1].$name = "CONFIG_MCSPI_SPI1_CS1"; mcspi1.mcspiChannel[1].advanced = true; mcspi1.mcspiChannel[1].bitRate = 20000000; mcspi1.mcspiChannel[1].CSn.rx = false; mcspi1.mcspiChannel[1].CSn.$assign = "SPI1_CS1";