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TDA4VH-Q1: Serdes assignment between SGMII and PCIe

Tony Tang
Mastermind 27372 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH, TDA4VM

Tool/software:

#1. Can TDA4VH PCIe work in 1 Lane mode? If Yes, can it support up to 4 x1Lane? 

#2. If #1 yes, Is there limitation on Serdes assignment between each PCIe instance? 

#3. On the EVM, QSGMII extension board used Serdes 5 and 7 for ENET-EXP-1, Serdes 6 and 8 for ENET-EXP-2, can it be any 2 pair of Serdes for one QSGMII, for example Serdes 5 and 6 for ENET-EXP-1, Serdes 7 and 8 for ENET-EXP-2?

#4, Besides the 2 QSGMII Serdes, can rest Serdes be used for PCIe instance? How many 1 Lane PCIe instance supported?

  • 0
    TI__Mastermind 36762 points

    Hi Tony,

    #1. Yes, PCIe can work in 1 Lane mode. No, it cannot support 4x1Lane. 

    #2. Yes, there is limitation with SERDES. Limitations are mentioned here: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/09_02_00_05/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SERDES/SERDES.html

    #3. Not on the EVM. There is a physical connection between each SERDES instance and ENET-EXP-1/2, so changes in software is not enough to change SERDES instance in use for ENET-EXP-1/2 on TI EVM. However, if the hardware is redesigned, then software supports the following muxes for SERDES: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/include/dt-bindings/mux/ti-serdes.h?h=ti-linux-6.1.y

    #4. At max, there can be 4 PCIe instances supported. As long as the SERDES lanes are not conflicting, yes, other SERDES lanes can be muxed for PCIe. For what each lane can be muxed as, the ti-serdes.h file is a good place to look.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    TI__Mastermind 27372 points

    Hi Takuma,

    Before I looking into details, want to confirm with you:

    Takuma Fujiwara said:
    Yes, PCIe can work in 1 Lane mode. No, it cannot support 4x1Lane. 

    Did not see PCIe 1 Lane mode in the datasheet table.

    TDA4VH has 4 PCIe port, and support 1 Lane mode, but can't support 4 1 Lane instance? How many 1 Lane PCIe instance can be supported? Customer want to extend PCIe interfaced ethernet PHY beside the QSGMII PHY.

    In the SDK user guide, has only one 4 Lane Serdes? not 2? Does it mean each SERDES module has 4 Lane. Just describe one Module here, as two module are identical?

    My customer's use case will be single Protocol Configuration: PCIe on SERDES 0/1,  S/QSGMII on SERDES2 and SERDES4 (why not 3). 

     What is PCIe port limitation here?

  • 0 in reply to Tony Tang
    TI__Mastermind 36762 points

    Hi Tony,

    Tony Tang said:
    TDA4VH has 4 PCIe port, and support 1 Lane mode, but can't support 4 1 Lane instance? How many 1 Lane PCIe instance can be supported? Customer want to extend PCIe interfaced ethernet PHY beside the QSGMII PHY.

    Apologies for the confusing wording. SERDES cannot support 4x1 Lane instance, but TDA4VH as a whole can support 4x1 Lane PCIe instance. Main limitation here is that SERDES can only support up to 2 interfaces, and there are in total 4 PCIe controllers on TDA4VH.

    Therefore, it is possible to have in total 4x1 Lane PCIe instance when using at least 2 instances of SERDES. On the other hand, it is not possible for 1 instance of SERDES to support 4 PCIe instances, due to the SERDES limitation.

    Tony Tang said:
    In the SDK user guide, has only one 4 Lane Serdes? not 2? Does it mean each SERDES module has 4 Lane. Just describe one Module here, as two module are identical?

    SERDES0, 1, 2, 4 are physically separate modules on the chip that can be muxed for different use cases, and these all have 4 lanes. The 4 lanes on each SERDES module can be split as 2x2Lanes or 1x4Lanes. 

    That is, 2 different interfaces that each uses up to 2 lanes (which includes 1 or 2 lane PCIe), or 1 interface that uses up to 4 lanes (so it can be 1, 2, or 4 lanes of PCIe).

    Note:The 2 Lane SERDES is only included on TDA4VM, so if there are mentions of 2 Lane SERDES then it is most likely an artifact from re-using documentation.

    Tony Tang said:

    My customer's use case will be single Protocol Configuration: PCIe on SERDES 0/1,  S/QSGMII on SERDES2 and SERDES4 (why not 3). 

    SERDES3 is also most likely an artifact from TDA4VM which had a lot more SERDES modules since each only had 2 lanes. What happened was:

    1. SERDES4 on TDA4VM is the same 4 lane SERDES module used in TDA4VH, so we did not modify
    2. 2 lane SERDES0~3 on TDA4VM is replaced by 4 lane SERDES on TDA4VH
    3. Since we switched from 2 lane modules to 4 lane modules, we no longer need as many SERDES instances -> we only need SERDES0, 1, 2
    4. Combined with the original SERDES4 instance, we get SERDES0,1,2,4 with no SERDES3.

    Regards,

    Takuma