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PCIe

Tommy Segerback
Prodigy 150 points

What does the ENDIVCLK bit in the PCI_SERDES_CFGPLL do ?

Should it be 0 or 1 ?

I am using 100MHz refclk and 2.5Mb/s

core clk is 1000MHz and CLKDIV4 is 1/3

Tommy

 

 

 

 

 

 

 

  • 0
    TI__Genius 12065 points

    Tommy,

    ENDIVCLK is used to enable a free running clock output, which runs at a fixed divide-by-5 of the internal PLL. 

    This clock output is switched off unless both the ENPLL and ENDIVCLK bits are set high (=1).  

    We may not care about the setup in this bit. But the default value 0x1C9 of PCIE_SERDES_CFGPLL (with ENDIVCLK=1) should be working fine with the refclk=100MHz.

     

    Sincerely,

    Steven