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Original question:

LP-AM243: QSPI flash doesn't meet timing

AM6421: OSPI Tap Delay - Input Reference to Output Divider Limits

Joe Paolino
Intellectual 610 points

Part Number: AM6421
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello,

I'm using QSPI with Internal Loopback.  As a result, I have disabled PHY Mode and am using Tap Mode.  Please help me to understand conflicting information between the Datasheet and Tech Ref.

The Datasheet indicates that OSPI0_CLK should be set to a divide by 4 of the internal reference for SDR mode:

The Tech Ref indicates that the fast reference clock should be running at least x4 the device clock

Can the processor run in Tap mode, SDR, with a reference clock divided by 6, 8, or greater?

Thank you,

Joe

  • 0
    TI__Guru**** 224085 points

    Hello Joe,

    Thank you for the query.

    I am reviewing the query and also reassigning the query to the expert to answer.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Expert 7145 points

    Greetings Joe,

    The OSPI module can be used in Tap SDR mode with the reference clock divided by 4,6,8... up to 32 (the /32 limit is the max the register setting allows). The /4 clock is the fastest you can run in Tap Mode and is the option the majority of our customers use.

    As far as actual frequency, the reference clock going to OSPI can only be clocked up to 200 MHz which should be reflected in our sysconfig tooling. This means that the datasheet timings (which show Tap Mode SDR going to up to 50 MHz) are also correct.

    Sincerely,

    Lucas

  • 0 in reply to Lucas Bowe
    Intellectual 610 points

    Hi Lucas,

    I think the terminology in the datasheet that appeared to conflict with the tech ref was the following: "OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers..."

    That would suggest to me that it must be a divide by 4.  Based on your comments, I would reinterpret that to mean OSPI0_CLK should be at least divided by 4 for SDR transfers.  Is that correct?

    Thank you,

    Joe

  • +1 in reply to Joe Paolino
    TI__Expert 7145 points

    Hey Joe,

    For the functionality of the IP, it should be at least divide by 4 for Tap SDR mode. The datasheet has to assume the highest frequency for a given mode when giving the timing and switching characteristics, which is likely why it states definitively it is a divide by 4. Understand the wording is a bit confusing.

    Sincerely,

    Lucas

  • 0 in reply to Lucas Bowe
    Intellectual 610 points

    Lucas, appreciate the prompt responses.  Thank you, Joe