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TDA4VM: Jacinto 7 Processor Power Distribution Networks: Implementation and Analysis (SPRACN5) missing

Marinus Holzner
Intellectual 1530 points
Part Number: TDA4VM
Other Parts Discussed in Thread: TDA4VL

Tool/software:

Hi team,

the TDA4VM datasheet is referring the "Jacinto 7 Processor Power Distribution Networks: Implementation and Analysis (SPRACN5)" document, but it is not linked in the datasheet nor can I find it online.

Can you provide me with the link please? or if not, can you tell me what other information we have about this topic right now?

Thank you,

Marinus

  • 0
    TI__Expert 6945 points

    The Jacinto 7 PDN application note (SPRACN5) has not been completed but the existing Sitara Processor Power Distribution Networks: Implementation and Analysis (SPRAC76F) covers all the same key design, stack-up & analysis topics.

    The Jacinto7 EVM board PCB stack-ups can be found within the EVM SOM design zip file. I see the TDA4VM EVM SOM design file is missing the 16-Lyr SOM PCB stack-up but the TDA4VL EVM SOM design file does have the 16-Lyr SOM PCB stack-up file which is same stack-up used for the TDA4VM SOM design.

    The Jacinto7 PCB PI Targets for each TDA4x SoC can be found within the App Note folder on CDDS under each J7 SoC.  I have included the TDA4VM PI target table below for your reference.

     

  • 0 in reply to Bill McCracken
    Prodigy 180 points

    Hi Bill,

    does TI have PDN requirements just for these 4 power rails? Are there any PDN requirements defined for other power rails?

    Thanks

    Libor

  • 0 in reply to Libor Krejca
    TI__Expert 6945 points

    The 4x power rails with PI Z targets have peak loads > 1A and load steps that can cause impactful transient supply undershoot/dips.  All other power rails have peak loads < 1A or draw consistent/average load currents that do not create impactful transient supply noise.

    All power rails should apply good PCB design practices (layer assignments, routing width/area to minimize IR-drop, component placement & low inductance via interface) for robust PDN performance.