SK-AM62A-LP: With same addr, MCU R5 write ddr and DM R5 read ddr failed

gongming li

Prodigy 50 points

Part Number: SK-AM62A-LP

Tool/software:

Dear all:

I wanna share data between MCU R5 and DM R5.

I use MCU R5 write ddr (from 0xffff_63c3 to 0xffff_ffff) and DM R5 read that. I failed!

From uart, i saw that MCU R5 can read all data waht i wrote (addr from 0xffff_63c3 to 0xffff_ffff).

But in DM R5, it seems like that i can only read part data from ddr，as shown in figure:

I do not write -1 in ddr (most is "-1").

To make sure that DM R5 read all data correctly , what should i do?

over 1 year ago

0 Nick Saulnier over 1 year ago

TI__Guru** 100740 points

Hello Gongming,

First off, did you make sure to reserve the shared memory region in the Linux devicetree file to make sure that Linux does not overwrite the data?

For more information about basic concepts around memory allocation, refer to the AM62A academy, multicore module:
https://dev.ti.com/tirex/explore/node?node=A__AJa64F6ctzZNbb.TYx4mCA__AM62A-ACADEMY__WeZ9SsL__LATEST

Another thing to ensure is that neither core is caching the shared memory region.

Regards,

Nick

0 gongming li over 1 year ago in reply to Nick Saulnier

Prodigy 50 points

Dear Nick Saulnier:

Only MCU r5 and DM R5 run, the linux do not run.

How to ensure that neither core is caching the shared memory region?

Thank you and look forward to your kind advice!

0 Nick Saulnier over 1 year ago in reply to gongming li

TI__Guru** 100740 points

Hello Gongming,

What OS will be running on the A53 cores in your final design?

How are you initializing your board? How are you performing the reads and the writes?

I am reassigning your thread to another team member to comment within the context of an MCU+ only multicore scenario.

Regards,

Nick

0 gongming li over 1 year ago in reply to Nick Saulnier

Prodigy 50 points

Dear Nick Saulnier:

According to your advice, i use non-cache on the shared memory region.

Now, DM R5 can read all the data that MCU R5 write.

Why is this happening?

What are the effects on the system if non-cache is used.

Which OS function may be problematic？

If i config regionA as non-cache, can other region still use cache by config it as cache in MPU?

Thank you and look forward to your kind advice!

+1 Nitika Verma over 1 year ago in reply to gongming li

TI__Expert 7385 points

Hi Gongming,

gongming li said:
Why is this happening?

This is done so that the processor does not use stale values due to caching. When an access to a cached memory region is made the processor can "remember" the value accessed. Accessing the same memory location returns the value it remembers (stored in the cache) without looking at the memory location.

To avoid this problem, we mark that address space as non-cached to ensure that the processor does get stale data from the cache.

gongming li said:
If i config regionA as non-cache, can other region still use cache by config it as cache in MPU?

Do you mean, if a larger MPU region is defined as cached and if you carve out a region from that and define it as non-cached, will the remaining region still be able to use the cache? - if this is your question, then the answer is yes. If not, can you please help me understand your question?

Regards,

Nitika

0 gongming li over 1 year ago in reply to Nitika Verma

Prodigy 50 points

Thank you for your kind advice!

Best wishes!

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SK-AM62A-LP: With same addr, MCU R5 write ddr and DM R5 read ddr failed