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AM3352: GPMC issues

Ethan Tian
Intellectual 1872 points

Part Number: AM3352

Tool/software:

Hi experts

Customer configuration GPMC, 8bit address is 00 01 02 03 04 05 06 07.... But 16bit is 00 02 04 06 08 0A..... That's it. 16bit address is not contiguous. The configuration of the device tree is different, except that the bank-width of the GPMC is configured as 1, which is 8bit, and as 2, which is 16bit. Then the FPGA reads that 8 bits are sequential addresses, and 16 bits are only even addresses. 

8bit:

16bit

When reading continuously, the chip selection is not continuous, and the read have very big latency, the actual read bandwidth is very low. Calculate a bandwidth of almost 2 M/s. 

what causes that
In addition, how to implement address-less reading

  • +1
    TI__Mastermind 30272 points

    Byte address in sequency, 16bit address in even order, that is right.

    From the timing, the code should be using integer data type accessing GPMC like this: temp= *(unsigned int *) address; 32bit access is divided into gpmc bus width automatically by GPMC. so you see continue 4 OE in 8bit, 2 OE in 16bit.

    For the throughput suggestions:

    #1.Optimize the GPMC timing parameter to short/quick as long as FPGA can accept.

    #2. Use EDMA if access in sequency.

    #3. Enable Cache to the GPMC address range if the use case permit.